1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/reset/ast2500-reset.h>
5 #include "ast2500.dtsi"
8 scu: clock-controller@1e6e2000 {
9 compatible = "aspeed,ast2500-scu";
10 reg = <0x1e6e2000 0x1000>;
16 rst: reset-controller {
18 compatible = "aspeed,ast2500-reset";
23 sdrammc: sdrammc@1e6e0000 {
25 compatible = "aspeed,ast2500-sdrammc";
26 reg = <0x1e6e0000 0x174
29 clocks = <&scu ASPEED_CLK_MPLL>;
30 resets = <&rst AST_RESET_SDRAM>;
39 sdhci0: sdhci@1e740100 {
40 compatible = "aspeed,ast2500-sdhci";
43 clocks = <&scu ASPEED_CLK_SDIO>;
44 resets = <&rst AST_RESET_SDIO>;
47 sdhci1: sdhci@1e740200 {
48 compatible = "aspeed,ast2500-sdhci";
51 clocks = <&scu ASPEED_CLK_SDIO>;
52 resets = <&rst AST_RESET_SDIO>;
60 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
64 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
68 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
72 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
76 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
84 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
88 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;