1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
5 * Copyright (C) 2012 Marvell
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78460 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78460 SoC";
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
44 clock-latency = <1000000>;
49 compatible = "marvell,sheeva-v7";
52 clock-latency = <1000000>;
57 compatible = "marvell,sheeva-v7";
60 clock-latency = <1000000>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
67 * configured as x4 or quad x1 lanes. Two units are
70 pciec: pcie@82000000 {
71 compatible = "marvell,armada-xp-pcie";
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
92 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
93 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
94 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
95 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
96 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
97 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
98 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
99 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
101 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
102 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
103 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
104 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
105 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
106 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
107 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
108 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
110 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
111 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
113 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
114 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
118 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
119 reg = <0x0800 0 0 0 0>;
120 #address-cells = <3>;
122 #interrupt-cells = <1>;
123 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
124 0x81000000 0 0 0x81000000 0x1 0 1 0>;
125 bus-range = <0x00 0xff>;
126 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0 0 0 0 &mpic 58>;
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <0>;
130 clocks = <&gateclk 5>;
131 resets = <&systemc 0 0>;
137 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
138 reg = <0x1000 0 0 0 0>;
139 #address-cells = <3>;
141 #interrupt-cells = <1>;
142 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
143 0x81000000 0 0 0x81000000 0x2 0 1 0>;
144 bus-range = <0x00 0xff>;
145 interrupt-map-mask = <0 0 0 0>;
146 interrupt-map = <0 0 0 0 &mpic 59>;
147 marvell,pcie-port = <0>;
148 marvell,pcie-lane = <1>;
149 clocks = <&gateclk 6>;
150 resets = <&systemc 0 0>;
156 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
157 reg = <0x1800 0 0 0 0>;
158 #address-cells = <3>;
160 #interrupt-cells = <1>;
161 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
162 0x81000000 0 0 0x81000000 0x3 0 1 0>;
163 bus-range = <0x00 0xff>;
164 interrupt-map-mask = <0 0 0 0>;
165 interrupt-map = <0 0 0 0 &mpic 60>;
166 marvell,pcie-port = <0>;
167 marvell,pcie-lane = <2>;
168 clocks = <&gateclk 7>;
169 resets = <&systemc 0 0>;
175 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
176 reg = <0x2000 0 0 0 0>;
177 #address-cells = <3>;
179 #interrupt-cells = <1>;
180 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
181 0x81000000 0 0 0x81000000 0x4 0 1 0>;
182 bus-range = <0x00 0xff>;
183 interrupt-map-mask = <0 0 0 0>;
184 interrupt-map = <0 0 0 0 &mpic 61>;
185 marvell,pcie-port = <0>;
186 marvell,pcie-lane = <3>;
187 clocks = <&gateclk 8>;
188 resets = <&systemc 0 0>;
194 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
195 reg = <0x2800 0 0 0 0>;
196 #address-cells = <3>;
198 #interrupt-cells = <1>;
199 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
200 0x81000000 0 0 0x81000000 0x5 0 1 0>;
201 bus-range = <0x00 0xff>;
202 interrupt-map-mask = <0 0 0 0>;
203 interrupt-map = <0 0 0 0 &mpic 62>;
204 marvell,pcie-port = <1>;
205 marvell,pcie-lane = <0>;
206 clocks = <&gateclk 9>;
207 resets = <&systemc 0 1>;
213 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
214 reg = <0x3000 0 0 0 0>;
215 #address-cells = <3>;
217 #interrupt-cells = <1>;
218 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
219 0x81000000 0 0 0x81000000 0x6 0 1 0>;
220 bus-range = <0x00 0xff>;
221 interrupt-map-mask = <0 0 0 0>;
222 interrupt-map = <0 0 0 0 &mpic 63>;
223 marvell,pcie-port = <1>;
224 marvell,pcie-lane = <1>;
225 clocks = <&gateclk 10>;
226 resets = <&systemc 0 1>;
232 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
233 reg = <0x3800 0 0 0 0>;
234 #address-cells = <3>;
236 #interrupt-cells = <1>;
237 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
238 0x81000000 0 0 0x81000000 0x7 0 1 0>;
239 bus-range = <0x00 0xff>;
240 interrupt-map-mask = <0 0 0 0>;
241 interrupt-map = <0 0 0 0 &mpic 64>;
242 marvell,pcie-port = <1>;
243 marvell,pcie-lane = <2>;
244 clocks = <&gateclk 11>;
245 resets = <&systemc 0 1>;
251 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
252 reg = <0x4000 0 0 0 0>;
253 #address-cells = <3>;
255 #interrupt-cells = <1>;
256 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
257 0x81000000 0 0 0x81000000 0x8 0 1 0>;
258 bus-range = <0x00 0xff>;
259 interrupt-map-mask = <0 0 0 0>;
260 interrupt-map = <0 0 0 0 &mpic 65>;
261 marvell,pcie-port = <1>;
262 marvell,pcie-lane = <3>;
263 clocks = <&gateclk 12>;
264 resets = <&systemc 0 1>;
270 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
271 reg = <0x4800 0 0 0 0>;
272 #address-cells = <3>;
274 #interrupt-cells = <1>;
275 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
276 0x81000000 0 0 0x81000000 0x9 0 1 0>;
277 bus-range = <0x00 0xff>;
278 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map = <0 0 0 0 &mpic 99>;
280 marvell,pcie-port = <2>;
281 marvell,pcie-lane = <0>;
282 clocks = <&gateclk 26>;
283 resets = <&systemc 0 2>;
289 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
290 reg = <0x5000 0 0 0 0>;
291 #address-cells = <3>;
293 #interrupt-cells = <1>;
294 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
295 0x81000000 0 0 0x81000000 0xa 0 1 0>;
296 bus-range = <0x00 0xff>;
297 interrupt-map-mask = <0 0 0 0>;
298 interrupt-map = <0 0 0 0 &mpic 103>;
299 marvell,pcie-port = <3>;
300 marvell,pcie-lane = <0>;
301 clocks = <&gateclk 27>;
302 resets = <&systemc 0 3>;
309 compatible = "marvell,armada-370-gpio",
310 "marvell,orion-gpio";
311 reg = <0x18100 0x40>, <0x181c0 0x08>;
312 reg-names = "gpio", "pwm";
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 interrupts = <82>, <83>, <84>, <85>;
320 clocks = <&coreclk 0>;
324 compatible = "marvell,armada-370-gpio",
325 "marvell,orion-gpio";
326 reg = <0x18140 0x40>, <0x181c8 0x08>;
327 reg-names = "gpio", "pwm";
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 interrupts = <87>, <88>, <89>, <90>;
335 clocks = <&coreclk 0>;
339 compatible = "marvell,armada-370-gpio",
340 "marvell,orion-gpio";
341 reg = <0x18180 0x40>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
350 eth3: ethernet@34000 {
351 compatible = "marvell,armada-xp-neta";
352 reg = <0x34000 0x4000>;
354 clocks = <&gateclk 1>;
362 compatible = "marvell,mv78460-pinctrl";