1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
5 * Copyright (C) 2012 Marvell
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78260 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78260 SoC";
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
43 clock-latency = <1000000>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
53 pciec: pcie@82000000 {
54 compatible = "marvell,armada-xp-pcie";
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
98 reg = <0x0800 0 0 0 0>;
101 #interrupt-cells = <1>;
102 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
103 0x81000000 0 0 0x81000000 0x1 0 1 0>;
104 bus-range = <0x00 0xff>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 58>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <0>;
109 clocks = <&gateclk 5>;
110 resets = <&systemc 0 0>;
116 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
117 reg = <0x1000 0 0 0 0>;
118 #address-cells = <3>;
120 #interrupt-cells = <1>;
121 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
122 0x81000000 0 0 0x81000000 0x2 0 1 0>;
123 bus-range = <0x00 0xff>;
124 interrupt-map-mask = <0 0 0 0>;
125 interrupt-map = <0 0 0 0 &mpic 59>;
126 marvell,pcie-port = <0>;
127 marvell,pcie-lane = <1>;
128 clocks = <&gateclk 6>;
129 resets = <&systemc 0 0>;
135 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
136 reg = <0x1800 0 0 0 0>;
137 #address-cells = <3>;
139 #interrupt-cells = <1>;
140 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
141 0x81000000 0 0 0x81000000 0x3 0 1 0>;
142 bus-range = <0x00 0xff>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &mpic 60>;
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <2>;
147 clocks = <&gateclk 7>;
148 resets = <&systemc 0 0>;
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
158 #interrupt-cells = <1>;
159 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
160 0x81000000 0 0 0x81000000 0x4 0 1 0>;
161 bus-range = <0x00 0xff>;
162 interrupt-map-mask = <0 0 0 0>;
163 interrupt-map = <0 0 0 0 &mpic 61>;
164 marvell,pcie-port = <0>;
165 marvell,pcie-lane = <3>;
166 clocks = <&gateclk 8>;
167 resets = <&systemc 0 0>;
173 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
174 reg = <0x2800 0 0 0 0>;
175 #address-cells = <3>;
177 #interrupt-cells = <1>;
178 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
179 0x81000000 0 0 0x81000000 0x5 0 1 0>;
180 bus-range = <0x00 0xff>;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 62>;
183 marvell,pcie-port = <1>;
184 marvell,pcie-lane = <0>;
185 clocks = <&gateclk 9>;
186 resets = <&systemc 0 1>;
192 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
193 reg = <0x3000 0 0 0 0>;
194 #address-cells = <3>;
196 #interrupt-cells = <1>;
197 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
198 0x81000000 0 0 0x81000000 0x6 0 1 0>;
199 bus-range = <0x00 0xff>;
200 interrupt-map-mask = <0 0 0 0>;
201 interrupt-map = <0 0 0 0 &mpic 63>;
202 marvell,pcie-port = <1>;
203 marvell,pcie-lane = <1>;
204 clocks = <&gateclk 10>;
205 resets = <&systemc 0 1>;
211 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
212 reg = <0x3800 0 0 0 0>;
213 #address-cells = <3>;
215 #interrupt-cells = <1>;
216 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
217 0x81000000 0 0 0x81000000 0x7 0 1 0>;
218 bus-range = <0x00 0xff>;
219 interrupt-map-mask = <0 0 0 0>;
220 interrupt-map = <0 0 0 0 &mpic 64>;
221 marvell,pcie-port = <1>;
222 marvell,pcie-lane = <2>;
223 clocks = <&gateclk 11>;
224 resets = <&systemc 0 1>;
230 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
231 reg = <0x4000 0 0 0 0>;
232 #address-cells = <3>;
234 #interrupt-cells = <1>;
235 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
236 0x81000000 0 0 0x81000000 0x8 0 1 0>;
237 bus-range = <0x00 0xff>;
238 interrupt-map-mask = <0 0 0 0>;
239 interrupt-map = <0 0 0 0 &mpic 65>;
240 marvell,pcie-port = <1>;
241 marvell,pcie-lane = <3>;
242 clocks = <&gateclk 12>;
243 resets = <&systemc 0 1>;
249 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
250 reg = <0x4800 0 0 0 0>;
251 #address-cells = <3>;
253 #interrupt-cells = <1>;
254 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
255 0x81000000 0 0 0x81000000 0x9 0 1 0>;
256 bus-range = <0x00 0xff>;
257 interrupt-map-mask = <0 0 0 0>;
258 interrupt-map = <0 0 0 0 &mpic 99>;
259 marvell,pcie-port = <2>;
260 marvell,pcie-lane = <0>;
261 clocks = <&gateclk 26>;
262 resets = <&systemc 0 2>;
269 compatible = "marvell,armada-370-gpio",
270 "marvell,orion-gpio";
271 reg = <0x18100 0x40>, <0x181c0 0x08>;
272 reg-names = "gpio", "pwm";
277 interrupt-controller;
278 #interrupt-cells = <2>;
279 interrupts = <82>, <83>, <84>, <85>;
280 clocks = <&coreclk 0>;
284 compatible = "marvell,armada-370-gpio",
285 "marvell,orion-gpio";
286 reg = <0x18140 0x40>, <0x181c8 0x08>;
287 reg-names = "gpio", "pwm";
292 interrupt-controller;
293 #interrupt-cells = <2>;
294 interrupts = <87>, <88>, <89>, <90>;
295 clocks = <&coreclk 0>;
299 compatible = "marvell,armada-370-gpio",
300 "marvell,orion-gpio";
301 reg = <0x18180 0x40>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
310 eth3: ethernet@34000 {
311 compatible = "marvell,armada-xp-neta";
312 reg = <0x34000 0x4000>;
314 clocks = <&gateclk 1>;
322 compatible = "marvell,mv78260-pinctrl";