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44 * Device Tree file for Marvell Armada CP110 Slave.
47 #include <dt-bindings/comphy/comphy_data.h>
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
60 compatible = "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 cps_ethernet: ethernet@0 {
65 compatible = "marvell,armada-7k-pp22";
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
67 clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
68 clock-names = "pp_clk", "gop_clk", "mg_clk";
73 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
80 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
87 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
94 cps_mdio: mdio@12a200 {
97 compatible = "marvell,orion-mdio";
98 reg = <0x12a200 0x10>;
101 cps_syscon0: system-controller@440000 {
102 compatible = "marvell,cp110-system-controller0",
104 reg = <0x440000 0x1000>;
106 core-clock-output-names =
107 "cps-apll", "cps-ppv2-core", "cps-eip",
108 "cps-core", "cps-nand-core";
109 gate-clock-output-names =
110 "cps-audio", "cps-communit", "cps-nand",
111 "cps-ppv2", "cps-sdio", "cps-mg-domain",
112 "cps-mg-core", "cps-xor1", "cps-xor0",
113 "cps-gop-dp", "none", "cps-pcie_x10",
114 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
115 "cps-sata", "cps-sata-usb", "cps-main",
116 "cps-sd-mmc", "none", "none",
117 "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
118 "cps-usb3dev", "cps-eip150", "cps-eip197";
121 cps_pinctl: cps-pinctl@440000 {
122 compatible = "marvell,mvebu-pinctrl",
123 "marvell,a80x0-cp1-pinctrl";
124 bank-name ="cp1-110";
125 reg = <0x440000 0x20>;
129 cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
130 marvell,pins = < 0 1 2 3 4 5 6 7
132 marvell,function = <3>;
134 cps_spi1_pins: cps-spi-pins-1 {
135 marvell,pins = < 13 14 15 16 >;
136 marvell,function = <3>;
140 cps_gpio0: gpio@440100 {
141 compatible = "marvell,orion-gpio";
142 reg = <0x440100 0x40>;
149 cps_gpio1: gpio@440140 {
150 compatible = "marvell,orion-gpio";
151 reg = <0x440140 0x40>;
158 cps_sata0: sata@540000 {
159 compatible = "marvell,armada-8k-ahci";
160 reg = <0x540000 0x30000>;
161 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&cps_syscon0 1 15>;
166 cps_usb3_0: usb3@500000 {
167 compatible = "marvell,armada-8k-xhci",
169 reg = <0x500000 0x4000>;
171 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&cps_syscon0 1 22>;
176 cps_usb3_1: usb3@510000 {
177 compatible = "marvell,armada-8k-xhci",
179 reg = <0x510000 0x4000>;
181 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cps_syscon0 1 23>;
186 cps_xor0: xor@6a0000 {
187 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
188 reg = <0x6a0000 0x1000>,
191 msi-parent = <&gic_v2m0>;
192 clocks = <&cps_syscon0 1 8>;
195 cps_xor1: xor@6c0000 {
196 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
197 reg = <0x6c0000 0x1000>,
200 msi-parent = <&gic_v2m0>;
201 clocks = <&cps_syscon0 1 7>;
204 cps_spi0: spi@700600 {
205 compatible = "marvell,armada-380-spi";
206 reg = <0x700600 0x50>;
207 #address-cells = <0x1>;
210 clocks = <&cps_syscon0 0 3>;
214 cps_spi1: spi@700680 {
215 compatible = "marvell,armada-380-spi";
216 reg = <0x700680 0x50>;
217 #address-cells = <1>;
220 clocks = <&cps_syscon0 1 21>;
224 cps_i2c0: i2c@701000 {
225 compatible = "marvell,mv78230-i2c";
226 reg = <0x701000 0x20>;
227 #address-cells = <1>;
229 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cps_syscon0 1 21>;
234 cps_i2c1: i2c@701100 {
235 compatible = "marvell,mv78230-i2c";
236 reg = <0x701100 0x20>;
237 #address-cells = <1>;
239 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cps_syscon0 1 21>;
244 cps_comphy: comphy@441000 {
245 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
246 reg = <0x441000 0x8>,
252 cps_utmi0: utmi@580000 {
253 compatible = "marvell,mvebu-utmi-2.6.0";
254 reg = <0x580000 0x1000>, /* utmi-unit */
255 <0x440420 0x4>, /* usb-cfg */
256 <0x440440 0x4>; /* utmi-cfg */
257 utmi-port = <UTMI_PHY_TO_USB_HOST0>;
262 cps_pcie0: pcie@f4600000 {
263 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
264 reg = <0 0xf4600000 0 0x10000>,
265 <0 0xfaf00000 0 0x80000>;
266 reg-names = "ctrl", "config";
267 #address-cells = <3>;
269 #interrupt-cells = <1>;
272 msi-parent = <&gic_v2m0>;
274 bus-range = <0 0xff>;
277 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
278 /* non-prefetchable memory */
279 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
280 interrupt-map-mask = <0 0 0 0>;
281 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
282 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cps_syscon0 1 13>;
288 cps_pcie1: pcie@f4620000 {
289 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
290 reg = <0 0xf4620000 0 0x10000>,
291 <0 0xfbf00000 0 0x80000>;
292 reg-names = "ctrl", "config";
293 #address-cells = <3>;
295 #interrupt-cells = <1>;
298 msi-parent = <&gic_v2m0>;
300 bus-range = <0 0xff>;
303 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
304 /* non-prefetchable memory */
305 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
306 interrupt-map-mask = <0 0 0 0>;
307 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
308 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cps_syscon0 1 11>;
315 cps_pcie2: pcie@f4640000 {
316 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
317 reg = <0 0xf4640000 0 0x10000>,
318 <0 0xfcf00000 0 0x80000>;
319 reg-names = "ctrl", "config";
320 #address-cells = <3>;
322 #interrupt-cells = <1>;
325 msi-parent = <&gic_v2m0>;
327 bus-range = <0 0xff>;
330 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
331 /* non-prefetchable memory */
332 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
333 interrupt-map-mask = <0 0 0 0>;
334 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
335 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cps_syscon0 1 12>;