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6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
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44 * Device Tree file for Marvell Armada CP110 Slave.
47 #include <dt-bindings/comphy/comphy_data.h>
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
60 compatible = "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 cps_ethernet: ethernet@0 {
65 compatible = "marvell,armada-7k-pp22";
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
67 clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
68 clock-names = "pp_clk", "gop_clk", "mg_clk";
73 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
80 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
87 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
94 cps_mdio: mdio@12a200 {
97 compatible = "marvell,orion-mdio";
98 reg = <0x12a200 0x10>;
99 device-name = "cps-mdio";
102 cps_syscon0: system-controller@440000 {
103 compatible = "marvell,cp110-system-controller0",
105 reg = <0x440000 0x1000>;
107 core-clock-output-names =
108 "cps-apll", "cps-ppv2-core", "cps-eip",
109 "cps-core", "cps-nand-core";
110 gate-clock-output-names =
111 "cps-audio", "cps-communit", "cps-nand",
112 "cps-ppv2", "cps-sdio", "cps-mg-domain",
113 "cps-mg-core", "cps-xor1", "cps-xor0",
114 "cps-gop-dp", "none", "cps-pcie_x10",
115 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
116 "cps-sata", "cps-sata-usb", "cps-main",
117 "cps-sd-mmc", "none", "none",
118 "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
119 "cps-usb3dev", "cps-eip150", "cps-eip197";
122 cps_pinctl: cps-pinctl@440000 {
123 compatible = "marvell,mvebu-pinctrl",
124 "marvell,armada-8k-cps-pinctrl";
125 bank-name ="cp1-110";
126 reg = <0x440000 0x20>;
130 cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
131 marvell,pins = < 0 1 2 3 4 5 6 7
133 marvell,function = <3>;
135 cps_spi1_pins: cps-spi-pins-1 {
136 marvell,pins = < 13 14 15 16 >;
137 marvell,function = <3>;
141 cps_gpio0: gpio@440100 {
142 compatible = "marvell,orion-gpio";
143 reg = <0x440100 0x40>;
150 cps_gpio1: gpio@440140 {
151 compatible = "marvell,orion-gpio";
152 reg = <0x440140 0x40>;
159 cps_sata0: sata@540000 {
160 compatible = "marvell,armada-8k-ahci";
161 reg = <0x540000 0x30000>;
162 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&cps_syscon0 1 15>;
167 cps_usb3_0: usb3@500000 {
168 compatible = "marvell,armada-8k-xhci",
170 reg = <0x500000 0x4000>;
172 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cps_syscon0 1 22>;
177 cps_usb3_1: usb3@510000 {
178 compatible = "marvell,armada-8k-xhci",
180 reg = <0x510000 0x4000>;
182 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cps_syscon0 1 23>;
187 cps_xor0: xor@6a0000 {
188 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
189 reg = <0x6a0000 0x1000>,
192 msi-parent = <&gic_v2m0>;
193 clocks = <&cps_syscon0 1 8>;
196 cps_xor1: xor@6c0000 {
197 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
198 reg = <0x6c0000 0x1000>,
201 msi-parent = <&gic_v2m0>;
202 clocks = <&cps_syscon0 1 7>;
205 cps_spi0: spi@700600 {
206 compatible = "marvell,armada-380-spi";
207 reg = <0x700600 0x50>;
208 #address-cells = <0x1>;
211 clocks = <&cps_syscon0 0 3>;
215 cps_spi1: spi@700680 {
216 compatible = "marvell,armada-380-spi";
217 reg = <0x700680 0x50>;
218 #address-cells = <1>;
221 clocks = <&cps_syscon0 1 21>;
225 cps_i2c0: i2c@701000 {
226 compatible = "marvell,mv78230-i2c";
227 reg = <0x701000 0x20>;
228 #address-cells = <1>;
230 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&cps_syscon0 1 21>;
235 cps_i2c1: i2c@701100 {
236 compatible = "marvell,mv78230-i2c";
237 reg = <0x701100 0x20>;
238 #address-cells = <1>;
240 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cps_syscon0 1 21>;
245 cps_comphy: comphy@441000 {
246 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
247 reg = <0x441000 0x8>,
253 cps_utmi0: utmi@580000 {
254 compatible = "marvell,mvebu-utmi-2.6.0";
255 reg = <0x580000 0x1000>, /* utmi-unit */
256 <0x440420 0x4>, /* usb-cfg */
257 <0x440440 0x4>; /* utmi-cfg */
258 utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
263 cps_pcie0: pcie@f4600000 {
264 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
265 reg = <0 0xf4600000 0 0x10000>,
266 <0 0xfaf00000 0 0x80000>;
267 reg-names = "ctrl", "config";
268 #address-cells = <3>;
270 #interrupt-cells = <1>;
273 msi-parent = <&gic_v2m0>;
275 bus-range = <0 0xff>;
278 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
279 /* non-prefetchable memory */
280 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
281 interrupt-map-mask = <0 0 0 0>;
282 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
283 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cps_syscon0 1 13>;
289 cps_pcie1: pcie@f4620000 {
290 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
291 reg = <0 0xf4620000 0 0x10000>,
292 <0 0xfbf00000 0 0x80000>;
293 reg-names = "ctrl", "config";
294 #address-cells = <3>;
296 #interrupt-cells = <1>;
299 msi-parent = <&gic_v2m0>;
301 bus-range = <0 0xff>;
304 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
305 /* non-prefetchable memory */
306 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
307 interrupt-map-mask = <0 0 0 0>;
308 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
309 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&cps_syscon0 1 11>;
316 cps_pcie2: pcie@f4640000 {
317 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
318 reg = <0 0xf4640000 0 0x10000>,
319 <0 0xfcf00000 0 0x80000>;
320 reg-names = "ctrl", "config";
321 #address-cells = <3>;
323 #interrupt-cells = <1>;
326 msi-parent = <&gic_v2m0>;
328 bus-range = <0 0xff>;
331 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
332 /* non-prefetchable memory */
333 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
334 interrupt-map-mask = <0 0 0 0>;
335 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
336 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&cps_syscon0 1 12>;