arch/arm/dts/armada-ap806.dtsi

   1 /*
   2  * Copyright (C) 2016 Marvell Technology Group Ltd.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPLv2 or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /*
  44  * Device Tree file for Marvell Armada AP806.
  45  */
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 /dts-v1/;
  50
  51 / {
  52         model = "Marvell Armada AP806";
  53         compatible = "marvell,armada-ap806";
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 serial0 = &uart0;
  59                 serial1 = &uart1;
  60         };
  61
  62         psci {
  63                 compatible = "arm,psci-0.2";
  64                 method = "smc";
  65         };
  66
  67         reserved-memory {
  68                 #address-cells = <2>;
  69                 #size-cells = <2>;
  70                 ranges;
  71
  72                 psci-area@4000000 {
  73                         reg = <0x0 0x4000000 0x0 0x200000>;
  74                         no-map;
  75                 };
  76         };
  77
  78         ap806 {
  79                 #address-cells = <2>;
  80                 #size-cells = <2>;
  81                 compatible = "simple-bus";
  82                 interrupt-parent = <&gic>;
  83                 ranges;
  84
  85                 config-space {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         compatible = "simple-bus";
  89                         ranges = <0x0 0x0 0xf0000000 0x1000000>;
  90
  91                         gic: interrupt-controller@210000 {
  92                                 compatible = "arm,gic-400";
  93                                 #interrupt-cells = <3>;
  94                                 #address-cells = <1>;
  95                                 #size-cells = <1>;
  96                                 ranges;
  97                                 interrupt-controller;
  98                                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  99                                 reg = <0x210000 0x10000>,
 100                                       <0x220000 0x20000>,
 101                                       <0x240000 0x20000>,
 102                                       <0x260000 0x20000>;
 103
 104                                 gic_v2m0: v2m@280000 {
 105                                         compatible = "arm,gic-v2m-frame";
 106                                         msi-controller;
 107                                         reg = <0x280000 0x1000>;
 108                                         arm,msi-base-spi = <160>;
 109                                         arm,msi-num-spis = <32>;
 110                                 };
 111                                 gic_v2m1: v2m@290000 {
 112                                         compatible = "arm,gic-v2m-frame";
 113                                         msi-controller;
 114                                         reg = <0x290000 0x1000>;
 115                                         arm,msi-base-spi = <192>;
 116                                         arm,msi-num-spis = <32>;
 117                                 };
 118                                 gic_v2m2: v2m@2a0000 {
 119                                         compatible = "arm,gic-v2m-frame";
 120                                         msi-controller;
 121                                         reg = <0x2a0000 0x1000>;
 122                                         arm,msi-base-spi = <224>;
 123                                         arm,msi-num-spis = <32>;
 124                                 };
 125                                 gic_v2m3: v2m@2b0000 {
 126                                         compatible = "arm,gic-v2m-frame";
 127                                         msi-controller;
 128                                         reg = <0x2b0000 0x1000>;
 129                                         arm,msi-base-spi = <256>;
 130                                         arm,msi-num-spis = <32>;
 131                                 };
 132                         };
 133
 134                         timer {
 135                                 compatible = "arm,armv8-timer";
 136                                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
 137                                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
 138                                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
 139                                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 140                         };
 141
 142                         odmi: odmi@300000 {
 143                                 compatible = "marvell,odmi-controller";
 144                                 interrupt-controller;
 145                                 msi-controller;
 146                                 marvell,odmi-frames = <4>;
 147                                 reg = <0x300000 0x4000>,
 148                                       <0x304000 0x4000>,
 149                                       <0x308000 0x4000>,
 150                                       <0x30C000 0x4000>;
 151                                 marvell,spi-base = <128>, <136>, <144>, <152>;
 152                         };
 153
 154                         ap_pinctl: ap-pinctl@6F4000 {
 155                                 compatible = "marvell,ap806-pinctrl";
 156                                 bank-name ="apn-806";
 157                                 reg = <0x6F4000 0x10>;
 158                                 pin-count = <20>;
 159                                 max-func = <3>;
 160
 161                                 ap_i2c0_pins: i2c-pins-0 {
 162                                         marvell,pins = < 4 5 >;
 163                                         marvell,function = <3>;
 164                                 };
 165                                 ap_emmc_pins: emmc-pins-0 {
 166                                         marvell,pins = < 0 1 2 3 4 5 6 7
 167                                                          8 9 10 >;
 168                                         marvell,function = <1>;
 169                                 };
 170                         };
 171
 172                         ap_gpio0: gpio@6F5040 {
 173                                 compatible = "marvell,orion-gpio";
 174                                 reg = <0x6F5040 0x40>;
 175                                 ngpios = <20>;
 176                                 gpio-controller;
 177                                 #gpio-cells = <2>;
 178                         };
 179
 180                         xor@400000 {
 181                                 compatible = "marvell,mv-xor-v2";
 182                                 reg = <0x400000 0x1000>,
 183                                       <0x410000 0x1000>;
 184                                 msi-parent = <&gic_v2m0>;
 185                                 dma-coherent;
 186                         };
 187
 188                         xor@420000 {
 189                                 compatible = "marvell,mv-xor-v2";
 190                                 reg = <0x420000 0x1000>,
 191                                       <0x430000 0x1000>;
 192                                 msi-parent = <&gic_v2m0>;
 193                                 dma-coherent;
 194                         };
 195
 196                         xor@440000 {
 197                                 compatible = "marvell,mv-xor-v2";
 198                                 reg = <0x440000 0x1000>,
 199                                       <0x450000 0x1000>;
 200                                 msi-parent = <&gic_v2m0>;
 201                                 dma-coherent;
 202                         };
 203
 204                         xor@460000 {
 205                                 compatible = "marvell,mv-xor-v2";
 206                                 reg = <0x460000 0x1000>,
 207                                       <0x470000 0x1000>;
 208                                 msi-parent = <&gic_v2m0>;
 209                                 dma-coherent;
 210                         };
 211
 212                         spi0: spi@510600 {
 213                                 compatible = "marvell,armada-380-spi";
 214                                 reg = <0x510600 0x50>;
 215                                 #address-cells = <1>;
 216                                 #size-cells = <0>;
 217                                 cell-index = <0>;
 218                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 219                                 clocks = <&ap_syscon 3>;
 220                                 status = "disabled";
 221                         };
 222
 223                         i2c0: i2c@511000 {
 224                                 compatible = "marvell,mv78230-i2c";
 225                                 reg = <0x511000 0x20>;
 226                                 #address-cells = <1>;
 227                                 #size-cells = <0>;
 228                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 229                                 timeout-ms = <1000>;
 230                                 clocks = <&ap_syscon 3>;
 231                                 status = "disabled";
 232                         };
 233
 234                         uart0: serial@512000 {
 235                                 compatible = "snps,dw-apb-uart";
 236                                 reg = <0x512000 0x100>;
 237                                 reg-shift = <2>;
 238                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 239                                 reg-io-width = <1>;
 240                                 clocks = <&ap_syscon 3>;
 241                                 status = "disabled";
 242                                 clock-frequency = <200000000>;
 243                         };
 244
 245                         uart1: serial@512100 {
 246                                 compatible = "snps,dw-apb-uart";
 247                                 reg = <0x512100 0x100>;
 248                                 reg-shift = <2>;
 249                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 250                                 reg-io-width = <1>;
 251                                 clocks = <&ap_syscon 3>;
 252                                 status = "disabled";
 253
 254                         };
 255
 256                         ap_sdhci0: sdhci@6e0000 {
 257                                 compatible = "marvell,armada-8k-sdhci";
 258                                 reg = <0x6e0000 0x300>;
 259                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 260                                 dma-coherent;
 261                                 status = "disabled";
 262                         };
 263
 264                         ap_syscon: system-controller@6f4000 {
 265                                 compatible = "marvell,ap806-system-controller",
 266                                              "syscon";
 267                                 #clock-cells = <1>;
 268                                 clock-output-names = "ap-cpu-cluster-0",
 269                                                      "ap-cpu-cluster-1",
 270                                                      "ap-fixed", "ap-mss";
 271                                 reg = <0x6f4000 0x1000>;
 272                         };
 273                 };
 274         };
 275 };