arch/arm/dts/armada-8040-puzzle-m801.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016 Marvell International Ltd.
   4  * Copyright (C) 2020 Sartura Ltd.
   5  */
   6
   7 #include "armada-8040.dtsi" /* include SoC device tree */
   8
   9 / {
  10         model = "iEi-Puzzle-M801";
  11         compatible = "marvell,armada8040-puzzle-m801",
  12                      "marvell,armada8040";
  13
  14         chosen {
  15                 stdout-path = "serial0:115200n8";
  16         };
  17
  18         aliases {
  19                 i2c0 = &ap_i2c0;
  20                 i2c1 = &cp0_i2c0;
  21                 i2c2 = &cp0_i2c1;
  22                 i2c3 = &i2c_switch;
  23                 spi0 = &ap_spi0;
  24                 gpio0 = &ap_gpio0;
  25                 gpio1 = &cp0_gpio0;
  26                 gpio2 = &cp0_gpio1;
  27                 gpio3 = &sfpplus_gpio;
  28         };
  29
  30         memory@00000000 {
  31                 device_type = "memory";
  32                 reg = <0x0 0x0 0x0 0x80000000>;
  33         };
  34
  35         simple-bus {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 reg_usb3h0_vbus: usb3-vbus0 {
  41                         compatible = "regulator-fixed";
  42                         pinctrl-names = "default";
  43                         pinctrl-0 = <&cp0_xhci_vbus_pins>;
  44                         regulator-name = "reg-usb3h0-vbus";
  45                         regulator-min-microvolt = <5000000>;
  46                         regulator-max-microvolt = <5000000>;
  47                         startup-delay-us = <500000>;
  48                         enable-active-high;
  49                         regulator-always-on;
  50                         regulator-boot-on;
  51                         gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
  52                 };
  53         };
  54 };
  55
  56 &ap_i2c0 {
  57         status = "okay";
  58         clock-frequency = <100000>;
  59
  60         rtc@32 {
  61                 compatible = "epson,rx8010";
  62                 reg = <0x32>;
  63         };
  64 };
  65
  66 &uart0 {
  67         status = "okay";
  68 };
  69
  70 &ap_pinctl {
  71         /*
  72          * MPP Bus:
  73          * AP SPI0 [0-3]
  74          * AP I2C [4-5]
  75          * AP GPIO [6]
  76          * AP UART 1 RX/TX [7-8]
  77          * AP GPIO [9-10]
  78          * AP GPIO [12]
  79          * UART0 [11,19]
  80          */
  81                   /* 0 1 2 3 4 5 6 7 8 9 */
  82         pin-func = < 3 3 3 3 3 3 3 3 3 0
  83                      0 3 0 0 0 0 0 0 0 3 >;
  84 };
  85
  86 &cp0_pinctl {
  87         /*
  88          * MPP Bus:
  89          * [0-31] = 0xff: Keep default CP0_shared_pins:
  90          * [11] CLKOUT_MPP_11 (out)
  91          * [23] LINK_RD_IN_CP2CP (in)
  92          * [25] CLKOUT_MPP_25 (out)
  93          * [29] AVS_FB_IN_CP2CP (in)
  94          * [32,34] SMI
  95          * [33]    MSS power down
  96          * [35-38] CP0 I2C1 and I2C0
  97          * [39] MSS CKE Enable
  98          * [40,41] CP0 UART1 TX/RX
  99          * [42,43] XSMI (controls two 10G phys)
 100          * [47] USB VBUS EN
 101          * [48] FAN PWM
 102          * [49] 10G port 1 interrupt
 103          * [50] 10G port 0 interrupt
 104          * [51] 2.5G SFP TX fault
 105          * [52] PCIe reset out
 106          * [53] 2.5G SFP mode
 107          * [54] 2.5G SFP LOS
 108          * [55] Micro SD card detect
 109          * [56-61] Micro SD
 110          * [62] CP1 SFI SFP FAULT
 111          */
 112                 /*   0    1    2    3    4    5    6    7    8    9 */
 113         pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 114                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 115                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 116                      0xff 0    7    0xa  7    2    2    2    2    0xa
 117                      7    7    8    8    0    0    0    0    0    0
 118                      0    0    0    0    0    0    0xe  0xe  0xe  0xe
 119                      0xe  0xe  0 >;
 120
 121         cp0_xhci_vbus_pins: cpm-xhci-vbus-pins {
 122                 marvell,pins = < 47 >;
 123                 marvell,function = <0>;
 124         };
 125
 126         cp0_pcie_reset_pins: cpm-pcie-reset-pins {
 127                 marvell,pins = < 52 >;
 128                 marvell,function = <0>;
 129         };
 130 };
 131
 132 &cp0_sdhci0 {
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&cp0_sdhci_pins>;
 135         bus-width= <4>;
 136         status = "okay";
 137 };
 138
 139 &cp0_pcie0 {
 140         num-lanes = <1>;
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&cp0_pcie_reset_pins>;
 143         marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
 144         status = "okay";
 145 };
 146
 147 &cp0_i2c0 {
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&cp0_i2c0_pins>;
 150         status = "okay";
 151         clock-frequency = <100000>;
 152
 153         sfpplus_gpio: gpio@21 {
 154                 compatible = "nxp,pca9555";
 155                 reg = <0x21>;
 156                 gpio-controller;
 157                 #gpio-cells = <2>;
 158         };
 159 };
 160
 161 &cp0_i2c1 {
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&cp0_i2c1_pins>;
 164         status = "okay";
 165         clock-frequency = <100000>;
 166
 167         i2c_switch: i2c-switch@70 {
 168                 compatible = "nxp,pca9544";
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171                 reg = <0x70>;
 172         };
 173 };
 174
 175 &cp0_sata0 {
 176         status = "okay";
 177 };
 178
 179 &cp0_ethernet {
 180         pinctrl-names = "default";
 181         status = "okay";
 182 };
 183
 184 &cp0_mdio {
 185         status = "okay";
 186         cp0_ge_phy0: ethernet-phy@1 {
 187                 reg = <0>;
 188         };
 189
 190         cp0_ge_phy1: ethernet-phy@2 {
 191                 reg = <1>;
 192         };
 193 };
 194
 195 &cp0_eth0 {
 196         status = "okay";
 197         phy-mode = "sfi";
 198 };
 199
 200 &cp0_eth1 {
 201         status = "okay";
 202         phy-mode = "sgmii";
 203         phy = <&cp0_ge_phy0>;
 204 };
 205
 206 &cp0_eth2 {
 207         status = "okay";
 208         phy-mode = "sgmii";
 209         phy = <&cp0_ge_phy1>;
 210 };
 211
 212 &cp0_comphy {
 213         /*
 214          * CP0 Serdes Configuration:
 215          * Lane 0: PCIe0 (x1)
 216          * Lane 1: SGMII2
 217          * Lane 2: SATA0
 218          * Lane 3: SGMII1
 219          * Lane 4: SFI (10G)
 220          * Lane 5: SATA1
 221          */
 222         phy0 {
 223                 phy-type = <COMPHY_TYPE_PEX0>;
 224         };
 225         phy1 {
 226                 phy-type = <COMPHY_TYPE_SGMII2>;
 227                 phy-speed = <COMPHY_SPEED_1_25G>;
 228         };
 229         phy2 {
 230                 phy-type = <COMPHY_TYPE_SATA0>;
 231         };
 232         phy3 {
 233                 phy-type = <COMPHY_TYPE_SGMII1>;
 234                 phy-speed = <COMPHY_SPEED_1_25G>;
 235         };
 236         phy4 {
 237                 phy-type = <COMPHY_TYPE_SFI0>;
 238         };
 239         phy5 {
 240                 phy-type = <COMPHY_TYPE_SATA1>;
 241         };
 242 };
 243
 244 &cp1_mdio {
 245         status = "okay";
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&cp1_smi_pins>;
 248
 249         cp1_ge_phy0: ethernet-phy@3 {
 250                 reg = <1>;
 251         };
 252
 253         cp1_ge_phy1: ethernet-phy@4 {
 254                 reg = <0>;
 255         };
 256 };
 257
 258 &cp1_pcie0 {
 259         num-lanes = <2>;
 260         pinctrl-names = "default";
 261         status = "okay";
 262 };
 263
 264 &cp1_usb3_0 {
 265         vbus-supply = <&reg_usb3h0_vbus>;
 266         status = "okay";
 267 };
 268
 269 &cp1_utmi0 {
 270         status = "okay";
 271 };
 272
 273 &cp1_ethernet {
 274         status = "okay";
 275 };
 276
 277 &cp1_eth0 {
 278         status = "okay";
 279         phy-mode = "sfi";
 280 };
 281
 282 &cp1_eth1 {
 283         status = "okay";
 284         phy = <&cp1_ge_phy0>;
 285         phy-mode = "sgmii";
 286 };
 287
 288 &cp1_eth2 {
 289         status = "okay";
 290         phy = <&cp1_ge_phy1>;
 291         phy-mode = "sgmii";
 292 };
 293
 294 &cp1_pinctl {
 295         /*
 296          * MPP Bus:
 297          * [0-5] TDM
 298          * [27-28] SMI
 299          * [29-30] CP1 MSS I2C
 300          * [6-26, 31] GPIO
 301          * [32-62] = 0xff: Keep default CP1_shared_pins:
 302          */
 303                 /*   0    1    2    3    4    5    6    7    8    9 */
 304         pin-func = < 0x4  0x4  0x4  0x4  0x4  0x4  0x0  0x0  0x0  0x0
 305                      0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
 306                      0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x8  0x8  0x8
 307                      0x8  0x0  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 308                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 309                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 310                      0xff 0xff 0xff>;
 311
 312         cp1_smi_pins: cp1-smi-pins {
 313                 marvell,pins = < 27 28 >;
 314                 marvell,function = <8>;
 315         };
 316 };
 317
 318 &ap_spi0 {
 319         status = "okay";
 320
 321         spi-flash@0 {
 322                 #address-cells = <1>;
 323                 #size-cells = <1>;
 324                 compatible = "jedec,spi-nor";
 325                 reg = <0>;
 326                 spi-max-frequency = <10000000>;
 327
 328                 partitions {
 329                         compatible = "fixed-partitions";
 330                         #address-cells = <1>;
 331                         #size-cells = <1>;
 332
 333                         partition@u-boot {
 334                                 reg = <0x00000000 0x001f0000>;
 335                                 label = "u-boot";
 336                         };
 337                         partition@u-boot-env {
 338                                 reg = <0x001f0000 0x00010000>;
 339                                 label = "u-boot-env";
 340                         };
 341                         partition@ubi1 {
 342                                 reg = <0x00200000 0x03f00000>;
 343                                 label = "ubi1";
 344                         };
 345                         partition@ubi2 {
 346                                 reg = <0x04100000 0x03f00000>;
 347                                 label = "ubi2";
 348                         };
 349                 };
 350         };
 351 };
 352
 353 &cp1_comphy {
 354         /*
 355          * CP1 Serdes Configuration:
 356          * Lane 0: PCIe0 (x2)
 357          * Lane 1: PCIe0 (x2)
 358          * Lane 2: USB HOST 0
 359          * Lane 3: SGMII1
 360          * Lane 4: SFI (10G)
 361          * Lane 5: SGMII2
 362          */
 363         phy0 {
 364                 phy-type = <COMPHY_TYPE_PEX0>;
 365         };
 366         phy1 {
 367                 phy-type = <COMPHY_TYPE_PEX0>;
 368         };
 369         phy2 {
 370                 phy-type = <COMPHY_TYPE_USB3_HOST0>;
 371         };
 372         phy3 {
 373                 phy-type = <COMPHY_TYPE_SGMII1>;
 374                 phy-speed = <COMPHY_SPEED_1_25G>;
 375         };
 376         phy4 {
 377                 phy-type = <COMPHY_TYPE_SFI0>;
 378         };
 379         phy5 {
 380                 phy-type = <COMPHY_TYPE_SGMII2>;
 381                 phy-speed = <COMPHY_SPEED_1_25G>;
 382         };
 383 };