2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
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26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
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44 * Device Tree file for Marvell Armada 8040 Development board platform
47 #include "armada-8040.dtsi"
50 model = "Marvell Armada 8040 DB board";
51 compatible = "marvell,armada8040-db", "marvell,armada8040",
52 "marvell,armada-ap806-quad", "marvell,armada-ap806";
55 stdout-path = "serial0:115200n8";
64 device_type = "memory";
65 reg = <0x0 0x0 0x0 0x80000000>;
69 /* Accessible over the mini-USB CON9 connector on the main board */
79 /* 0 1 2 3 4 5 6 7 8 9 */
80 pin-func = < 1 1 1 1 1 1 1 1 1 1
81 1 3 0 0 0 0 0 0 0 3 >;
85 pinctrl-names = "default";
86 pinctrl-0 = <&ap_emmc_pins>;
93 * [0-31] = 0xff: Keep default CP0_shared_pins
94 * [11] CLKOUT_MPP_11 (out)
95 * [23] LINK_RD_IN_CP2CP (in)
96 * [25] CLKOUT_MPP_25 (out)
97 * [29] AVS_FB_IN_CP2CP (in)
99 * [33] GPIO: GE_INT#/push button/Wake
100 * [35] MSS_GPIO[3]: MSS_PWDN
101 * [36] MSS_GPIO[5]: MSS_VTT_EN
104 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
105 * [42-43] XG_MDC/XG_MDIO (XSMI)
109 /* 0 1 2 3 4 5 6 7 8 9 */
110 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
111 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
112 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
113 0xff 0xff 0x7 0x0 0x7 0xa 0xa 0x2 0x2 0x5
114 0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1
115 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
120 /* Serdes Configuration:
129 phy-type = <PHY_TYPE_PEX0>;
132 phy-type = <PHY_TYPE_SATA0>;
135 phy-type = <PHY_TYPE_SFI>;
138 phy-type = <PHY_TYPE_SATA1>;
141 phy-type = <PHY_TYPE_USB3_HOST1>;
144 phy-type = <PHY_TYPE_PEX2>;
148 /* CON6 on CP0 expansion */
157 /* CON5 on CP0 expansion */
163 pinctrl-names = "default";
164 pinctrl-0 = <&cpm_i2c0_pins>;
166 clock-frequency = <100000>;
169 /* CON4 on CP0 expansion */
174 /* CON9 on CP0 expansion */
179 /* CON10 on CP0 expansion */
193 pinctrl-names = "default";
194 pinctrl-0 = <&cpm_sdhci_pins>;
203 * [27,31] GE_MDIO/MDC
204 * [28] SATA1_PRESENT_ACTIVEn
206 * [32-62] = 0xff: Keep default CP1_shared_pins
208 /* 0 1 2 3 4 5 6 7 8 9 */
209 pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
210 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
211 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0x9 0xa
212 0xA 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
213 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
214 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
219 /* Serdes Configuration:
228 phy-type = <PHY_TYPE_PEX0>;
231 phy-type = <PHY_TYPE_SATA0>;
234 phy-type = <PHY_TYPE_SFI>;
237 phy-type = <PHY_TYPE_SATA1>;
240 phy-type = <PHY_TYPE_PEX1>;
243 phy-type = <PHY_TYPE_PEX2>;
247 /* CON6 on CP1 expansion */
256 /* CON5 on CP1 expansion */
262 pinctrl-names = "default";
263 pinctrl-0 = <&cps_spi1_pins>;
267 #address-cells = <1>;
269 compatible = "jedec,spi-nor";
271 spi-max-frequency = <10000000>;
274 compatible = "fixed-partitions";
275 #address-cells = <1>;
283 label = "Filesystem";
284 reg = <0x200000 0xce0000>;
290 /* CON4 on CP1 expansion */
295 /* CON9 on CP1 expansion */
300 /* CON10 on CP1 expansion */
310 phy1: ethernet-phy@1 {
322 phy-mode = "rgmii-id";