arch/arm/dts/armada-7040-db.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016- 2021 Marvell International Ltd.
   4  */
   5
   6 /*
   7  * Device Tree file for Marvell Armada 7040 Development board platform
   8  * Boot device: SPI NOR, 0x32 (SW3)
   9  */
  10
  11 #include "armada-7040.dtsi"
  12
  13 / {
  14         model = "Marvell Armada 7040 DB board";
  15         compatible = "marvell,armada7040-db", "marvell,armada7040",
  16                      "marvell,armada-ap806-quad", "marvell,armada-ap806";
  17
  18         chosen {
  19                 stdout-path = "serial0:115200n8";
  20         };
  21
  22         aliases {
  23                 i2c0 = &cp0_i2c0;
  24                 spi0 = &cp0_spi1;
  25         };
  26
  27         memory@00000000 {
  28                 device_type = "memory";
  29                 reg = <0x0 0x0 0x0 0x80000000>;
  30         };
  31 };
  32
  33 &ap_pinctl {
  34            /* MPP Bus:
  35             * SDIO  [0-5]
  36             * UART0 [11,19]
  37             */
  38                   /* 0 1 2 3 4 5 6 7 8 9 */
  39         pin-func = < 1 1 1 1 1 1 0 0 0 0
  40                      0 3 0 0 0 0 0 0 0 3 >;
  41 };
  42
  43 &uart0 {
  44         status = "okay";
  45 };
  46
  47
  48 &cp0_pcie2 {
  49         status = "okay";
  50 };
  51
  52 &cp0_i2c0 {
  53         pinctrl-names = "default";
  54         pinctrl-0 = <&cp0_i2c0_pins>;
  55         status = "okay";
  56         clock-frequency = <100000>;
  57 };
  58
  59 &cp0_pinctl {
  60                 /* MPP Bus:
  61                  * TDM   [0-11]
  62                  * SPI   [13-16]
  63                  * SATA1 [28]
  64                  * UART0 [29-30]
  65                  * SMI   [32,34]
  66                  * XSMI  [35-36]
  67                  * I2C   [37-38]
  68                  * RGMII1[44-55]
  69                  * SD    [56-62]
  70                  */
  71                 /*   0   1   2   3   4   5   6   7   8   9 */
  72         pin-func = < 4   4   4   4   4   4   4   4   4   4
  73                      4   4   0   3   3   3   3   0   0   0
  74                      0   0   0   0   0   0   0   0   9   0xA
  75                      0xA 0   7   0   7   7   7   2   2   0
  76                      0   0   0   0   1   1   1   1   1   1
  77                      1   1   1   1   1   1   0xE 0xE 0xE 0xE
  78                      0xE 0xE 0xE >;
  79 };
  80
  81 &cp0_spi1 {
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&cp0_spi0_pins>;
  84         status = "okay";
  85
  86         spi-flash@0 {
  87                 #address-cells = <0x1>;
  88                 #size-cells = <0x1>;
  89                 compatible = "jedec,spi-nor";
  90                 reg = <0x0>;
  91                 spi-max-frequency = <20000000>;
  92
  93                 partitions {
  94                         compatible = "fixed-partitions";
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97
  98                         partition@0 {
  99                                 label = "U-Boot";
 100                                 reg = <0x0 0x200000>;
 101                         };
 102
 103                         partition@400000 {
 104                                 label = "Filesystem";
 105                                 reg = <0x200000 0xe00000>;
 106                         };
 107                 };
 108         };
 109 };
 110
 111 &cp0_sata0 {
 112         status = "okay";
 113 };
 114
 115 &cp0_usb3_0 {
 116         status = "okay";
 117 };
 118
 119 &cp0_usb3_1 {
 120         status = "okay";
 121 };
 122
 123 &cp0_comphy {
 124         phy0 {
 125                 phy-type = <COMPHY_TYPE_SGMII1>;
 126                 phy-speed = <COMPHY_SPEED_1_25G>;
 127         };
 128
 129         phy1 {
 130                 phy-type = <COMPHY_TYPE_USB3_HOST0>;
 131                 phy-speed = <COMPHY_SPEED_5G>;
 132         };
 133
 134         phy2 {
 135                 phy-type = <COMPHY_TYPE_SFI0>;
 136                 phy-speed = <COMPHY_SPEED_10_3125G>;
 137         };
 138
 139         phy3 {
 140                 phy-type = <COMPHY_TYPE_SATA1>;
 141                 phy-speed = <COMPHY_SPEED_5G>;
 142         };
 143
 144         phy4 {
 145                 phy-type = <COMPHY_TYPE_USB3_HOST1>;
 146                 phy-speed = <COMPHY_SPEED_5G>;
 147         };
 148
 149         phy5 {
 150                 phy-type = <COMPHY_TYPE_PEX2>;
 151                 phy-speed = <COMPHY_SPEED_5G>;
 152         };
 153 };
 154
 155 &cp0_utmi0 {
 156         status = "okay";
 157 };
 158
 159 &cp0_utmi1 {
 160         status = "okay";
 161 };
 162
 163 &ap_sdhci0 {
 164         status = "okay";
 165         bus-width = <4>;
 166         no-1-8-v;
 167         non-removable;
 168 };
 169
 170 &cp0_sdhci0 {
 171         status = "okay";
 172         bus-width = <4>;
 173         no-1-8-v;
 174         non-removable;
 175 };
 176
 177 &cp0_mdio {
 178         phy0: ethernet-phy@0 {
 179                 reg = <0>;
 180         };
 181         phy1: ethernet-phy@1 {
 182                 reg = <1>;
 183         };
 184 };
 185
 186 &cp0_ethernet {
 187         status = "okay";
 188 };
 189
 190 &cp0_eth0 {
 191         status = "okay";
 192         phy-mode = "sfi"; /* lane-2 */
 193 };
 194
 195 &cp0_eth1 {
 196         status = "okay";
 197         phy = <&phy0>;
 198         phy-mode = "sgmii";
 199 };
 200
 201 &cp0_eth2 {
 202         status = "okay";
 203         phy = <&phy1>;
 204         phy-mode = "rgmii-id";
 205 };