2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 * Copyright (C) 2016 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/comphy/comphy_data.h>
49 #include <dt-bindings/gpio/gpio.h>
52 model = "Marvell Armada 37xx SoC";
53 compatible = "marvell,armada3700";
54 interrupt-parent = <&gic>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
74 compatible = "arm,psci-0.2";
79 compatible = "arm,armv8-timer";
80 interrupts = <GIC_PPI 13
81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
87 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
91 compatible = "simple-bus";
99 compatible = "simple-bus";
100 /* 32M internal register @ 0xd000_0000 */
101 ranges = <0x0 0x0 0xd0000000 0x2000000>;
103 uart0: serial@12000 {
104 compatible = "marvell,armada-3700-uart";
105 reg = <0x12000 0x400>;
106 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 wdt: watchdog-timer@8300 {
111 compatible = "marvell,armada-3700-wdt";
116 nb_periph_clk: nb-periph-clk@13000 {
117 compatible = "marvell,armada-3700-periph-clock-nb";
118 reg = <0x13000 0x100>;
119 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
123 sb_periph_clk: sb-periph-clk@18000 {
124 compatible = "marvell,armada-3700-periph-clock-sb";
125 reg = <0x18000 0x100>;
126 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
131 compatible = "marvell,armada-3700-tbg-clock";
132 reg = <0x13200 0x100>;
136 pinctrl_nb: pinctrl-nb@13800 {
137 compatible = "marvell,armada3710-nb-pinctrl",
138 "syscon", "simple-mfd";
139 reg = <0x13800 0x100>, <0x13C00 0x20>;
142 gpio-ranges = <&pinctrl_nb 0 0 36>;
145 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
160 spi_quad_pins: spi-quad-pins {
165 i2c1_pins: i2c1-pins {
170 i2c2_pins: i2c2-pins {
175 uart1_pins: uart1-pins {
180 uart2_pins: uart2-pins {
191 pinctrl_sb: pinctrl-sb@18800 {
192 compatible = "marvell,armada3710-sb-pinctrl",
193 "syscon", "simple-mfd";
194 reg = <0x18800 0x100>, <0x18C00 0x20>;
197 gpio-ranges = <&pinctrl_sb 0 0 30>;
200 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
207 rgmii_pins: mii-pins {
217 sdio_pins: sdio-pins {
222 pcie_pins: pcie-pins {
229 compatible = "marvell,armada3700-xhci",
231 reg = <0x58000 0x4000>;
232 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
237 compatible = "marvell,armada3700-ehci";
238 reg = <0x5e000 0x450>;
243 compatible = "marvell,armada-3700-xor";
248 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
251 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
255 sdhci0: sdhci@d0000 {
256 compatible = "marvell,armada-3700-sdhci",
257 "marvell,sdhci-xenon";
263 sdhci1: sdhci@d8000 {
264 compatible = "marvell,armada-3700-sdhci",
265 "marvell,sdhci-xenon";
272 compatible = "marvell,armada-3700-ahci";
273 reg = <0xe0000 0x2000>;
274 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
278 gic: interrupt-controller@1d00000 {
279 compatible = "arm,gic-v3";
280 #interrupt-cells = <3>;
281 interrupt-controller;
282 reg = <0x1d00000 0x10000>, /* GICD */
283 <0x1d40000 0x40000>; /* GICR */
287 compatible = "marvell,armada-3700-neta";
288 reg = <0x30000 0x20>;
293 compatible = "marvell,armada-3700-neta";
294 reg = <0x40000 0x20>;
299 compatible = "marvell,armada-3700-i2c";
300 reg = <0x11000 0x100>;
305 compatible = "marvell,armada-3700-spi";
306 reg = <0x10600 0x50>;
307 #address-cells = <1>;
310 spi-max-frequency = <50000000>;
311 clocks = <&nb_periph_clk 7>;
315 comphy: comphy@18300 {
316 compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
317 reg = <0x18300 0x28>,
320 mux-lane-order = <1 0 2>;
325 pcie0: pcie@d0070000 {
326 compatible = "marvell,armada-3700-pcie";
327 reg = <0 0xd0070000 0 0x20000>;
328 #address-cells = <3>;
334 bus-range = <0 0xff>;
336 * The 128 MiB address range [0xe8000000-0xf0000000] is
337 * dedicated for PCIe and can be assigned to 8 windows
338 * with size a power of two. Use one 64 KiB window for
339 * IO at the end and the remaining seven windows
340 * (totaling 127 MiB) for MEM.
342 ranges = <0x82000000 0 0xe8000000
343 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
344 0x81000000 0 0xefff0000
345 0 0xefff0000 0 0x10000>; /* Port 0 IO*/