2 * Device Tree Include file for Marvell Armada 375 family SoC
4 * Copyright (C) 2014 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "skeleton.dtsi"
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
56 model = "Marvell Armada 375 family SoC";
57 compatible = "marvell,armada375";
68 /* 2 GHz fixed main PLL */
70 compatible = "fixed-clock";
72 clock-frequency = <1000000000>;
74 /* 25 MHz reference crystal */
76 compatible = "fixed-clock";
78 clock-frequency = <25000000>;
85 enable-method = "marvell,armada-375-smp";
89 compatible = "arm,cortex-a9";
94 compatible = "arm,cortex-a9";
100 compatible = "arm,cortex-a9-pmu";
101 interrupts-extended = <&mpic 3>;
105 compatible = "marvell,armada375-mbus", "simple-bus";
107 #address-cells = <2>;
109 controller = <&mbusc>;
110 interrupt-parent = <&gic>;
111 pcie-mem-aperture = <0xe0000000 0x8000000>;
112 pcie-io-aperture = <0xe8000000 0x100000>;
115 compatible = "marvell,bootrom";
116 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
120 compatible = "marvell,mvebu-devbus";
121 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
122 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
123 #address-cells = <1>;
125 clocks = <&coreclk 0>;
130 compatible = "marvell,mvebu-devbus";
131 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
132 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
133 #address-cells = <1>;
135 clocks = <&coreclk 0>;
140 compatible = "marvell,mvebu-devbus";
141 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
142 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
143 #address-cells = <1>;
145 clocks = <&coreclk 0>;
150 compatible = "marvell,mvebu-devbus";
151 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
152 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
153 #address-cells = <1>;
155 clocks = <&coreclk 0>;
160 compatible = "marvell,mvebu-devbus";
161 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
162 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
163 #address-cells = <1>;
165 clocks = <&coreclk 0>;
170 compatible = "simple-bus";
172 #address-cells = <1>;
174 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
176 L2: cache-controller@8000 {
177 compatible = "arm,pl310-cache";
178 reg = <0x8000 0x1000>;
181 arm,double-linefill-incr = <1>;
182 arm,double-linefill-wrap = <0>;
183 arm,double-linefill = <1>;
188 compatible = "arm,cortex-a9-scu";
193 compatible = "arm,cortex-a9-twd-timer";
195 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
196 clocks = <&coreclk 2>;
199 gic: interrupt-controller@d000 {
200 compatible = "arm,cortex-a9-gic";
201 #interrupt-cells = <3>;
203 interrupt-controller;
204 reg = <0xd000 0x1000>,
209 #address-cells = <1>;
211 compatible = "marvell,orion-mdio";
213 clocks = <&gateclk 19>;
216 /* Network controller */
218 compatible = "marvell,armada-375-pp2";
219 reg = <0xf0000 0xa000>, /* Packet Processor regs */
220 <0xc0000 0x3060>, /* LMS regs */
221 <0xc4000 0x100>, /* eth0 regs */
222 <0xc5000 0x100>; /* eth1 regs */
223 clocks = <&gateclk 3>, <&gateclk 19>;
224 clock-names = "pp_clk", "gop_clk";
228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
234 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
241 compatible = "marvell,orion-rtc";
242 reg = <0x10300 0x20>;
243 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
247 compatible = "marvell,armada-375-spi",
249 reg = <0x10600 0x50>;
250 #address-cells = <1>;
253 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&coreclk 0>;
259 compatible = "marvell,armada-375-spi",
261 reg = <0x10680 0x50>;
262 #address-cells = <1>;
265 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&coreclk 0>;
271 compatible = "marvell,mv64xxx-i2c";
272 reg = <0x11000 0x20>;
273 #address-cells = <1>;
275 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&coreclk 0>;
282 compatible = "marvell,mv64xxx-i2c";
283 reg = <0x11100 0x20>;
284 #address-cells = <1>;
286 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&coreclk 0>;
292 uart0: serial@12000 {
293 compatible = "snps,dw-apb-uart";
294 reg = <0x12000 0x100>;
296 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&coreclk 0>;
302 uart1: serial@12100 {
303 compatible = "snps,dw-apb-uart";
304 reg = <0x12100 0x100>;
306 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&coreclk 0>;
313 compatible = "marvell,mv88f6720-pinctrl";
314 reg = <0x18000 0x24>;
316 i2c0_pins: i2c0-pins {
317 marvell,pins = "mpp14", "mpp15";
318 marvell,function = "i2c0";
321 i2c1_pins: i2c1-pins {
322 marvell,pins = "mpp61", "mpp62";
323 marvell,function = "i2c1";
326 nand_pins: nand-pins {
327 marvell,pins = "mpp0", "mpp1", "mpp2",
328 "mpp3", "mpp4", "mpp5",
329 "mpp6", "mpp7", "mpp8",
330 "mpp9", "mpp10", "mpp11",
332 marvell,function = "nand";
335 sdio_pins: sdio-pins {
336 marvell,pins = "mpp24", "mpp25", "mpp26",
337 "mpp27", "mpp28", "mpp29";
338 marvell,function = "sd";
341 spi0_pins: spi0-pins {
342 marvell,pins = "mpp0", "mpp1", "mpp4",
343 "mpp5", "mpp8", "mpp9";
344 marvell,function = "spi0";
349 compatible = "marvell,orion-gpio";
350 reg = <0x18100 0x40>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
363 compatible = "marvell,orion-gpio";
364 reg = <0x18140 0x40>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
377 compatible = "marvell,orion-gpio";
378 reg = <0x18180 0x40>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
387 systemc: system-controller@18200 {
388 compatible = "marvell,armada-375-system-controller";
389 reg = <0x18200 0x100>;
393 gateclk: clock-gating-control@18220 {
394 compatible = "marvell,armada-375-gating-clock";
396 clocks = <&coreclk 0>;
400 usbcluster: usb-cluster@18400 {
401 compatible = "marvell,armada-375-usb-cluster";
406 mbusc: mbus-controller@20000 {
407 compatible = "marvell,mbus-controller";
408 reg = <0x20000 0x100>, <0x20180 0x20>;
411 mpic: interrupt-controller@20a00 {
412 compatible = "marvell,mpic";
413 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
414 #interrupt-cells = <1>;
416 interrupt-controller;
418 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
422 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
423 reg = <0x20300 0x30>, <0x21040 0x30>;
424 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
425 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
426 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
427 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
430 clocks = <&coreclk 0>, <&refclk>;
431 clock-names = "nbclk", "fixed";
435 compatible = "marvell,armada-375-wdt";
436 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
437 clocks = <&coreclk 0>, <&refclk>;
438 clock-names = "nbclk", "fixed";
442 compatible = "marvell,armada-370-cpu-reset";
443 reg = <0x20800 0x10>;
446 coherency-fabric@21010 {
447 compatible = "marvell,armada-375-coherency-fabric";
448 reg = <0x21010 0x1c>;
452 compatible = "marvell,orion-ehci";
453 reg = <0x50000 0x500>;
454 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&gateclk 18>;
456 phys = <&usbcluster PHY_TYPE_USB2>;
462 compatible = "marvell,orion-ehci";
463 reg = <0x54000 0x500>;
464 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&gateclk 26>;
470 compatible = "marvell,armada-375-xhci";
471 reg = <0x58000 0x20000>,<0x5b880 0x80>;
472 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gateclk 16>;
474 phys = <&usbcluster PHY_TYPE_USB3>;
480 compatible = "marvell,orion-xor";
483 clocks = <&gateclk 22>;
487 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
492 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
500 compatible = "marvell,orion-xor";
503 clocks = <&gateclk 23>;
507 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
512 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
520 compatible = "marvell,armada-375-crypto";
521 reg = <0x90000 0x10000>;
523 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&gateclk 30>, <&gateclk 31>,
526 <&gateclk 28>, <&gateclk 29>;
527 clock-names = "cesa0", "cesa1",
529 marvell,crypto-srams = <&crypto_sram0>,
531 marvell,crypto-sram-size = <0x800>;
535 compatible = "marvell,orion-sata";
536 reg = <0xa0000 0x5000>;
537 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&gateclk 14>, <&gateclk 20>;
539 clock-names = "0", "1";
544 compatible = "marvell,armada370-nand";
545 reg = <0xd0000 0x54>;
546 #address-cells = <1>;
548 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&gateclk 11>;
554 compatible = "marvell,orion-sdio";
555 reg = <0xd4000 0x200>;
556 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&gateclk 17>;
566 compatible = "marvell,armada375-thermal";
567 reg = <0xe8078 0x4>, <0xe807c 0x8>;
571 coreclk: mvebu-sar@e8204 {
572 compatible = "marvell,armada-375-core-clock";
573 reg = <0xe8204 0x04>;
577 coredivclk: corediv-clock@e8250 {
578 compatible = "marvell,armada-375-corediv-clock";
582 clock-output-names = "nand";
586 pciec: pcie@82000000 {
587 compatible = "marvell,armada-370-pcie";
591 #address-cells = <3>;
594 msi-parent = <&mpic>;
595 bus-range = <0x00 0xff>;
598 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
599 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
600 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
601 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
602 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
603 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
607 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
608 reg = <0x0800 0 0 0 0>;
609 #address-cells = <3>;
611 #interrupt-cells = <1>;
612 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
613 0x81000000 0 0 0x81000000 0x1 0 1 0>;
614 bus-range = <0x00 0xff>;
615 interrupt-map-mask = <0 0 0 0>;
616 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
617 marvell,pcie-port = <0>;
618 marvell,pcie-lane = <0>;
619 clocks = <&gateclk 5>;
620 resets = <&systemc 0 0>;
626 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
627 reg = <0x1000 0 0 0 0>;
628 #address-cells = <3>;
630 #interrupt-cells = <1>;
631 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
632 0x81000000 0 0 0x81000000 0x2 0 1 0>;
633 bus-range = <0x00 0xff>;
634 interrupt-map-mask = <0 0 0 0>;
635 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
636 marvell,pcie-port = <0>;
637 marvell,pcie-lane = <1>;
638 clocks = <&gateclk 6>;
639 resets = <&systemc 0 1>;
645 crypto_sram0: sa-sram0 {
646 compatible = "mmio-sram";
647 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
648 clocks = <&gateclk 30>;
649 #address-cells = <1>;
651 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
654 crypto_sram1: sa-sram1 {
655 compatible = "mmio-sram";
656 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
657 clocks = <&gateclk 31>;
658 #address-cells = <1>;
660 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;