arch/arm/dts/am43xx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for AM43xx clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &scm_clocks {
   8         sys_clkin_ck: sys_clkin_ck {
   9                 #clock-cells = <0>;
  10                 compatible = "ti,mux-clock";
  11                 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
  12                 ti,bit-shift = <31>;
  13                 reg = <0x0040>;
  14         };
  15
  16         crystal_freq_sel_ck: crystal_freq_sel_ck {
  17                 #clock-cells = <0>;
  18                 compatible = "ti,mux-clock";
  19                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  20                 ti,bit-shift = <29>;
  21                 reg = <0x0040>;
  22         };
  23
  24         sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
  25                 #clock-cells = <0>;
  26                 compatible = "ti,mux-clock";
  27                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  28                 ti,bit-shift = <22>;
  29                 reg = <0x0040>;
  30         };
  31
  32         adc_tsc_fck: adc_tsc_fck {
  33                 #clock-cells = <0>;
  34                 compatible = "fixed-factor-clock";
  35                 clocks = <&sys_clkin_ck>;
  36                 clock-mult = <1>;
  37                 clock-div = <1>;
  38         };
  39
  40         dcan0_fck: dcan0_fck {
  41                 #clock-cells = <0>;
  42                 compatible = "fixed-factor-clock";
  43                 clocks = <&sys_clkin_ck>;
  44                 clock-mult = <1>;
  45                 clock-div = <1>;
  46         };
  47
  48         dcan1_fck: dcan1_fck {
  49                 #clock-cells = <0>;
  50                 compatible = "fixed-factor-clock";
  51                 clocks = <&sys_clkin_ck>;
  52                 clock-mult = <1>;
  53                 clock-div = <1>;
  54         };
  55
  56         mcasp0_fck: mcasp0_fck {
  57                 #clock-cells = <0>;
  58                 compatible = "fixed-factor-clock";
  59                 clocks = <&sys_clkin_ck>;
  60                 clock-mult = <1>;
  61                 clock-div = <1>;
  62         };
  63
  64         mcasp1_fck: mcasp1_fck {
  65                 #clock-cells = <0>;
  66                 compatible = "fixed-factor-clock";
  67                 clocks = <&sys_clkin_ck>;
  68                 clock-mult = <1>;
  69                 clock-div = <1>;
  70         };
  71
  72         smartreflex0_fck: smartreflex0_fck {
  73                 #clock-cells = <0>;
  74                 compatible = "fixed-factor-clock";
  75                 clocks = <&sys_clkin_ck>;
  76                 clock-mult = <1>;
  77                 clock-div = <1>;
  78         };
  79
  80         smartreflex1_fck: smartreflex1_fck {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-factor-clock";
  83                 clocks = <&sys_clkin_ck>;
  84                 clock-mult = <1>;
  85                 clock-div = <1>;
  86         };
  87
  88         sha0_fck: sha0_fck {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-factor-clock";
  91                 clocks = <&sys_clkin_ck>;
  92                 clock-mult = <1>;
  93                 clock-div = <1>;
  94         };
  95
  96         aes0_fck: aes0_fck {
  97                 #clock-cells = <0>;
  98                 compatible = "fixed-factor-clock";
  99                 clocks = <&sys_clkin_ck>;
 100                 clock-mult = <1>;
 101                 clock-div = <1>;
 102         };
 103
 104         ehrpwm0_tbclk: ehrpwm0_tbclk {
 105                 #clock-cells = <0>;
 106                 compatible = "ti,gate-clock";
 107                 clocks = <&l4ls_gclk>;
 108                 ti,bit-shift = <0>;
 109                 reg = <0x0664>;
 110         };
 111
 112         ehrpwm1_tbclk: ehrpwm1_tbclk {
 113                 #clock-cells = <0>;
 114                 compatible = "ti,gate-clock";
 115                 clocks = <&l4ls_gclk>;
 116                 ti,bit-shift = <1>;
 117                 reg = <0x0664>;
 118         };
 119
 120         ehrpwm2_tbclk: ehrpwm2_tbclk {
 121                 #clock-cells = <0>;
 122                 compatible = "ti,gate-clock";
 123                 clocks = <&l4ls_gclk>;
 124                 ti,bit-shift = <2>;
 125                 reg = <0x0664>;
 126         };
 127
 128         ehrpwm3_tbclk: ehrpwm3_tbclk {
 129                 #clock-cells = <0>;
 130                 compatible = "ti,gate-clock";
 131                 clocks = <&l4ls_gclk>;
 132                 ti,bit-shift = <4>;
 133                 reg = <0x0664>;
 134         };
 135
 136         ehrpwm4_tbclk: ehrpwm4_tbclk {
 137                 #clock-cells = <0>;
 138                 compatible = "ti,gate-clock";
 139                 clocks = <&l4ls_gclk>;
 140                 ti,bit-shift = <5>;
 141                 reg = <0x0664>;
 142         };
 143
 144         ehrpwm5_tbclk: ehrpwm5_tbclk {
 145                 #clock-cells = <0>;
 146                 compatible = "ti,gate-clock";
 147                 clocks = <&l4ls_gclk>;
 148                 ti,bit-shift = <6>;
 149                 reg = <0x0664>;
 150         };
 151 };
 152 &prcm_clocks {
 153         clk_32768_ck: clk_32768_ck {
 154                 #clock-cells = <0>;
 155                 compatible = "fixed-clock";
 156                 clock-frequency = <32768>;
 157         };
 158
 159         clk_rc32k_ck: clk_rc32k_ck {
 160                 #clock-cells = <0>;
 161                 compatible = "fixed-clock";
 162                 clock-frequency = <32768>;
 163         };
 164
 165         virt_19200000_ck: virt_19200000_ck {
 166                 #clock-cells = <0>;
 167                 compatible = "fixed-clock";
 168                 clock-frequency = <19200000>;
 169         };
 170
 171         virt_24000000_ck: virt_24000000_ck {
 172                 #clock-cells = <0>;
 173                 compatible = "fixed-clock";
 174                 clock-frequency = <24000000>;
 175         };
 176
 177         virt_25000000_ck: virt_25000000_ck {
 178                 #clock-cells = <0>;
 179                 compatible = "fixed-clock";
 180                 clock-frequency = <25000000>;
 181         };
 182
 183         virt_26000000_ck: virt_26000000_ck {
 184                 #clock-cells = <0>;
 185                 compatible = "fixed-clock";
 186                 clock-frequency = <26000000>;
 187         };
 188
 189         tclkin_ck: tclkin_ck {
 190                 #clock-cells = <0>;
 191                 compatible = "fixed-clock";
 192                 clock-frequency = <26000000>;
 193         };
 194
 195         dpll_core_ck: dpll_core_ck {
 196                 #clock-cells = <0>;
 197                 compatible = "ti,am3-dpll-core-clock";
 198                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 199                 reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
 200         };
 201
 202         dpll_core_x2_ck: dpll_core_x2_ck {
 203                 #clock-cells = <0>;
 204                 compatible = "ti,am3-dpll-x2-clock";
 205                 clocks = <&dpll_core_ck>;
 206         };
 207
 208         dpll_core_m4_ck: dpll_core_m4_ck {
 209                 #clock-cells = <0>;
 210                 compatible = "ti,divider-clock";
 211                 clocks = <&dpll_core_x2_ck>;
 212                 ti,max-div = <31>;
 213                 ti,autoidle-shift = <8>;
 214                 reg = <0x2d38>;
 215                 ti,index-starts-at-one;
 216                 ti,invert-autoidle-bit;
 217         };
 218
 219         dpll_core_m5_ck: dpll_core_m5_ck {
 220                 #clock-cells = <0>;
 221                 compatible = "ti,divider-clock";
 222                 clocks = <&dpll_core_x2_ck>;
 223                 ti,max-div = <31>;
 224                 ti,autoidle-shift = <8>;
 225                 reg = <0x2d3c>;
 226                 ti,index-starts-at-one;
 227                 ti,invert-autoidle-bit;
 228         };
 229
 230         dpll_core_m6_ck: dpll_core_m6_ck {
 231                 #clock-cells = <0>;
 232                 compatible = "ti,divider-clock";
 233                 clocks = <&dpll_core_x2_ck>;
 234                 ti,max-div = <31>;
 235                 ti,autoidle-shift = <8>;
 236                 reg = <0x2d40>;
 237                 ti,index-starts-at-one;
 238                 ti,invert-autoidle-bit;
 239         };
 240
 241         dpll_mpu_ck: dpll_mpu_ck {
 242                 #clock-cells = <0>;
 243                 compatible = "ti,am3-dpll-clock";
 244                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 245                 reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
 246         };
 247
 248         dpll_mpu_m2_ck: dpll_mpu_m2_ck {
 249                 #clock-cells = <0>;
 250                 compatible = "ti,divider-clock";
 251                 clocks = <&dpll_mpu_ck>;
 252                 ti,max-div = <31>;
 253                 ti,autoidle-shift = <8>;
 254                 reg = <0x2d70>;
 255                 ti,index-starts-at-one;
 256                 ti,invert-autoidle-bit;
 257         };
 258
 259         dpll_ddr_ck: dpll_ddr_ck {
 260                 #clock-cells = <0>;
 261                 compatible = "ti,am3-dpll-clock";
 262                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 263                 reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
 264         };
 265
 266         dpll_ddr_m2_ck: dpll_ddr_m2_ck {
 267                 #clock-cells = <0>;
 268                 compatible = "ti,divider-clock";
 269                 clocks = <&dpll_ddr_ck>;
 270                 ti,max-div = <31>;
 271                 ti,autoidle-shift = <8>;
 272                 reg = <0x2db0>;
 273                 ti,index-starts-at-one;
 274                 ti,invert-autoidle-bit;
 275         };
 276
 277         dpll_disp_ck: dpll_disp_ck {
 278                 #clock-cells = <0>;
 279                 compatible = "ti,am3-dpll-clock";
 280                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 281                 reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
 282         };
 283
 284         dpll_disp_m2_ck: dpll_disp_m2_ck {
 285                 #clock-cells = <0>;
 286                 compatible = "ti,divider-clock";
 287                 clocks = <&dpll_disp_ck>;
 288                 ti,max-div = <31>;
 289                 ti,autoidle-shift = <8>;
 290                 reg = <0x2e30>;
 291                 ti,index-starts-at-one;
 292                 ti,invert-autoidle-bit;
 293                 ti,set-rate-parent;
 294         };
 295
 296         dpll_per_ck: dpll_per_ck {
 297                 #clock-cells = <0>;
 298                 compatible = "ti,am3-dpll-j-type-clock";
 299                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 300                 reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
 301         };
 302
 303         dpll_per_m2_ck: dpll_per_m2_ck {
 304                 #clock-cells = <0>;
 305                 compatible = "ti,divider-clock";
 306                 clocks = <&dpll_per_ck>;
 307                 ti,max-div = <127>;
 308                 ti,autoidle-shift = <8>;
 309                 reg = <0x2df0>;
 310                 ti,index-starts-at-one;
 311                 ti,invert-autoidle-bit;
 312         };
 313
 314         dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
 315                 #clock-cells = <0>;
 316                 compatible = "fixed-factor-clock";
 317                 clocks = <&dpll_per_m2_ck>;
 318                 clock-mult = <1>;
 319                 clock-div = <4>;
 320         };
 321
 322         dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
 323                 #clock-cells = <0>;
 324                 compatible = "fixed-factor-clock";
 325                 clocks = <&dpll_per_m2_ck>;
 326                 clock-mult = <1>;
 327                 clock-div = <4>;
 328         };
 329
 330         clk_24mhz: clk_24mhz {
 331                 #clock-cells = <0>;
 332                 compatible = "fixed-factor-clock";
 333                 clocks = <&dpll_per_m2_ck>;
 334                 clock-mult = <1>;
 335                 clock-div = <8>;
 336         };
 337
 338         clkdiv32k_ck: clkdiv32k_ck {
 339                 #clock-cells = <0>;
 340                 compatible = "fixed-factor-clock";
 341                 clocks = <&clk_24mhz>;
 342                 clock-mult = <1>;
 343                 clock-div = <732>;
 344         };
 345
 346         clkdiv32k_ick: clkdiv32k_ick {
 347                 #clock-cells = <0>;
 348                 compatible = "ti,gate-clock";
 349                 clocks = <&clkdiv32k_ck>;
 350                 ti,bit-shift = <8>;
 351                 reg = <0x2a38>;
 352         };
 353
 354         sysclk_div: sysclk_div {
 355                 #clock-cells = <0>;
 356                 compatible = "fixed-factor-clock";
 357                 clocks = <&dpll_core_m4_ck>;
 358                 clock-mult = <1>;
 359                 clock-div = <1>;
 360         };
 361
 362         pruss_ocp_gclk: pruss_ocp_gclk {
 363                 #clock-cells = <0>;
 364                 compatible = "ti,mux-clock";
 365                 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
 366                 reg = <0x4248>;
 367         };
 368
 369         clk_32k_tpm_ck: clk_32k_tpm_ck {
 370                 #clock-cells = <0>;
 371                 compatible = "fixed-clock";
 372                 clock-frequency = <32768>;
 373         };
 374
 375         timer1_fck: timer1_fck {
 376                 #clock-cells = <0>;
 377                 compatible = "ti,mux-clock";
 378                 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 379                 reg = <0x4200>;
 380         };
 381
 382         timer2_fck: timer2_fck {
 383                 #clock-cells = <0>;
 384                 compatible = "ti,mux-clock";
 385                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 386                 reg = <0x4204>;
 387         };
 388
 389         timer3_fck: timer3_fck {
 390                 #clock-cells = <0>;
 391                 compatible = "ti,mux-clock";
 392                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 393                 reg = <0x4208>;
 394         };
 395
 396         timer4_fck: timer4_fck {
 397                 #clock-cells = <0>;
 398                 compatible = "ti,mux-clock";
 399                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 400                 reg = <0x420c>;
 401         };
 402
 403         timer5_fck: timer5_fck {
 404                 #clock-cells = <0>;
 405                 compatible = "ti,mux-clock";
 406                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 407                 reg = <0x4210>;
 408         };
 409
 410         timer6_fck: timer6_fck {
 411                 #clock-cells = <0>;
 412                 compatible = "ti,mux-clock";
 413                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 414                 reg = <0x4214>;
 415         };
 416
 417         timer7_fck: timer7_fck {
 418                 #clock-cells = <0>;
 419                 compatible = "ti,mux-clock";
 420                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 421                 reg = <0x4218>;
 422         };
 423
 424         wdt1_fck: wdt1_fck {
 425                 #clock-cells = <0>;
 426                 compatible = "ti,mux-clock";
 427                 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
 428                 reg = <0x422c>;
 429         };
 430
 431         l3_gclk: l3_gclk {
 432                 #clock-cells = <0>;
 433                 compatible = "fixed-factor-clock";
 434                 clocks = <&dpll_core_m4_ck>;
 435                 clock-mult = <1>;
 436                 clock-div = <1>;
 437         };
 438
 439         dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
 440                 #clock-cells = <0>;
 441                 compatible = "fixed-factor-clock";
 442                 clocks = <&sysclk_div>;
 443                 clock-mult = <1>;
 444                 clock-div = <2>;
 445         };
 446
 447         l4hs_gclk: l4hs_gclk {
 448                 #clock-cells = <0>;
 449                 compatible = "fixed-factor-clock";
 450                 clocks = <&dpll_core_m4_ck>;
 451                 clock-mult = <1>;
 452                 clock-div = <1>;
 453         };
 454
 455         l3s_gclk: l3s_gclk {
 456                 #clock-cells = <0>;
 457                 compatible = "fixed-factor-clock";
 458                 clocks = <&dpll_core_m4_div2_ck>;
 459                 clock-mult = <1>;
 460                 clock-div = <1>;
 461         };
 462
 463         l4ls_gclk: l4ls_gclk {
 464                 #clock-cells = <0>;
 465                 compatible = "fixed-factor-clock";
 466                 clocks = <&dpll_core_m4_div2_ck>;
 467                 clock-mult = <1>;
 468                 clock-div = <1>;
 469         };
 470
 471         cpsw_125mhz_gclk: cpsw_125mhz_gclk {
 472                 #clock-cells = <0>;
 473                 compatible = "fixed-factor-clock";
 474                 clocks = <&dpll_core_m5_ck>;
 475                 clock-mult = <1>;
 476                 clock-div = <2>;
 477         };
 478
 479         cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
 480                 #clock-cells = <0>;
 481                 compatible = "ti,mux-clock";
 482                 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
 483                 reg = <0x4238>;
 484         };
 485
 486         clk_32k_mosc_ck: clk_32k_mosc_ck {
 487                 #clock-cells = <0>;
 488                 compatible = "fixed-clock";
 489                 clock-frequency = <32768>;
 490         };
 491
 492         gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
 493                 #clock-cells = <0>;
 494                 compatible = "ti,mux-clock";
 495                 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
 496                 reg = <0x4240>;
 497         };
 498
 499         gpio0_dbclk: gpio0_dbclk {
 500                 #clock-cells = <0>;
 501                 compatible = "ti,gate-clock";
 502                 clocks = <&gpio0_dbclk_mux_ck>;
 503                 ti,bit-shift = <8>;
 504                 reg = <0x2b68>;
 505         };
 506
 507         gpio1_dbclk: gpio1_dbclk {
 508                 #clock-cells = <0>;
 509                 compatible = "ti,gate-clock";
 510                 clocks = <&clkdiv32k_ick>;
 511                 ti,bit-shift = <8>;
 512                 reg = <0x8c78>;
 513         };
 514
 515         gpio2_dbclk: gpio2_dbclk {
 516                 #clock-cells = <0>;
 517                 compatible = "ti,gate-clock";
 518                 clocks = <&clkdiv32k_ick>;
 519                 ti,bit-shift = <8>;
 520                 reg = <0x8c80>;
 521         };
 522
 523         gpio3_dbclk: gpio3_dbclk {
 524                 #clock-cells = <0>;
 525                 compatible = "ti,gate-clock";
 526                 clocks = <&clkdiv32k_ick>;
 527                 ti,bit-shift = <8>;
 528                 reg = <0x8c88>;
 529         };
 530
 531         gpio4_dbclk: gpio4_dbclk {
 532                 #clock-cells = <0>;
 533                 compatible = "ti,gate-clock";
 534                 clocks = <&clkdiv32k_ick>;
 535                 ti,bit-shift = <8>;
 536                 reg = <0x8c90>;
 537         };
 538
 539         gpio5_dbclk: gpio5_dbclk {
 540                 #clock-cells = <0>;
 541                 compatible = "ti,gate-clock";
 542                 clocks = <&clkdiv32k_ick>;
 543                 ti,bit-shift = <8>;
 544                 reg = <0x8c98>;
 545         };
 546
 547         mmc_clk: mmc_clk {
 548                 #clock-cells = <0>;
 549                 compatible = "fixed-factor-clock";
 550                 clocks = <&dpll_per_m2_ck>;
 551                 clock-mult = <1>;
 552                 clock-div = <2>;
 553         };
 554
 555         gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
 556                 #clock-cells = <0>;
 557                 compatible = "ti,mux-clock";
 558                 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
 559                 ti,bit-shift = <1>;
 560                 reg = <0x423c>;
 561         };
 562
 563         gfx_fck_div_ck: gfx_fck_div_ck {
 564                 #clock-cells = <0>;
 565                 compatible = "ti,divider-clock";
 566                 clocks = <&gfx_fclk_clksel_ck>;
 567                 reg = <0x423c>;
 568                 ti,max-div = <2>;
 569         };
 570
 571         disp_clk: disp_clk {
 572                 #clock-cells = <0>;
 573                 compatible = "ti,mux-clock";
 574                 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
 575                 reg = <0x4244>;
 576                 ti,set-rate-parent;
 577         };
 578
 579         dpll_extdev_ck: dpll_extdev_ck {
 580                 #clock-cells = <0>;
 581                 compatible = "ti,am3-dpll-clock";
 582                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 583                 reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
 584         };
 585
 586         dpll_extdev_m2_ck: dpll_extdev_m2_ck {
 587                 #clock-cells = <0>;
 588                 compatible = "ti,divider-clock";
 589                 clocks = <&dpll_extdev_ck>;
 590                 ti,max-div = <127>;
 591                 ti,autoidle-shift = <8>;
 592                 reg = <0x2e70>;
 593                 ti,index-starts-at-one;
 594                 ti,invert-autoidle-bit;
 595         };
 596
 597         mux_synctimer32k_ck: mux_synctimer32k_ck {
 598                 #clock-cells = <0>;
 599                 compatible = "ti,mux-clock";
 600                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
 601                 reg = <0x4230>;
 602         };
 603
 604         synctimer_32kclk: synctimer_32kclk {
 605                 #clock-cells = <0>;
 606                 compatible = "ti,gate-clock";
 607                 clocks = <&mux_synctimer32k_ck>;
 608                 ti,bit-shift = <8>;
 609                 reg = <0x2a30>;
 610         };
 611
 612         timer8_fck: timer8_fck {
 613                 #clock-cells = <0>;
 614                 compatible = "ti,mux-clock";
 615                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 616                 reg = <0x421c>;
 617         };
 618
 619         timer9_fck: timer9_fck {
 620                 #clock-cells = <0>;
 621                 compatible = "ti,mux-clock";
 622                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 623                 reg = <0x4220>;
 624         };
 625
 626         timer10_fck: timer10_fck {
 627                 #clock-cells = <0>;
 628                 compatible = "ti,mux-clock";
 629                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 630                 reg = <0x4224>;
 631         };
 632
 633         timer11_fck: timer11_fck {
 634                 #clock-cells = <0>;
 635                 compatible = "ti,mux-clock";
 636                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 637                 reg = <0x4228>;
 638         };
 639
 640         cpsw_50m_clkdiv: cpsw_50m_clkdiv {
 641                 #clock-cells = <0>;
 642                 compatible = "fixed-factor-clock";
 643                 clocks = <&dpll_core_m5_ck>;
 644                 clock-mult = <1>;
 645                 clock-div = <1>;
 646         };
 647
 648         cpsw_5m_clkdiv: cpsw_5m_clkdiv {
 649                 #clock-cells = <0>;
 650                 compatible = "fixed-factor-clock";
 651                 clocks = <&cpsw_50m_clkdiv>;
 652                 clock-mult = <1>;
 653                 clock-div = <10>;
 654         };
 655
 656         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 657                 #clock-cells = <0>;
 658                 compatible = "ti,am3-dpll-x2-clock";
 659                 clocks = <&dpll_ddr_ck>;
 660         };
 661
 662         dpll_ddr_m4_ck: dpll_ddr_m4_ck {
 663                 #clock-cells = <0>;
 664                 compatible = "ti,divider-clock";
 665                 clocks = <&dpll_ddr_x2_ck>;
 666                 ti,max-div = <31>;
 667                 ti,autoidle-shift = <8>;
 668                 reg = <0x2db8>;
 669                 ti,index-starts-at-one;
 670                 ti,invert-autoidle-bit;
 671         };
 672
 673         dpll_per_clkdcoldo: dpll_per_clkdcoldo {
 674                 #clock-cells = <0>;
 675                 compatible = "ti,fixed-factor-clock";
 676                 clocks = <&dpll_per_ck>;
 677                 ti,clock-mult = <1>;
 678                 ti,clock-div = <1>;
 679                 ti,autoidle-shift = <8>;
 680                 reg = <0x2e14>;
 681                 ti,invert-autoidle-bit;
 682         };
 683
 684         dll_aging_clk_div: dll_aging_clk_div {
 685                 #clock-cells = <0>;
 686                 compatible = "ti,divider-clock";
 687                 clocks = <&sys_clkin_ck>;
 688                 reg = <0x4250>;
 689                 ti,dividers = <8>, <16>, <32>;
 690         };
 691
 692         div_core_25m_ck: div_core_25m_ck {
 693                 #clock-cells = <0>;
 694                 compatible = "fixed-factor-clock";
 695                 clocks = <&sysclk_div>;
 696                 clock-mult = <1>;
 697                 clock-div = <8>;
 698         };
 699
 700         func_12m_clk: func_12m_clk {
 701                 #clock-cells = <0>;
 702                 compatible = "fixed-factor-clock";
 703                 clocks = <&dpll_per_m2_ck>;
 704                 clock-mult = <1>;
 705                 clock-div = <16>;
 706         };
 707
 708         vtp_clk_div: vtp_clk_div {
 709                 #clock-cells = <0>;
 710                 compatible = "fixed-factor-clock";
 711                 clocks = <&sys_clkin_ck>;
 712                 clock-mult = <1>;
 713                 clock-div = <2>;
 714         };
 715
 716         usbphy_32khz_clkmux: usbphy_32khz_clkmux {
 717                 #clock-cells = <0>;
 718                 compatible = "ti,mux-clock";
 719                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 720                 reg = <0x4260>;
 721         };
 722
 723         usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
 724                 #clock-cells = <0>;
 725                 compatible = "ti,gate-clock";
 726                 clocks = <&usbphy_32khz_clkmux>;
 727                 ti,bit-shift = <8>;
 728                 reg = <0x2a40>;
 729         };
 730
 731         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
 732                 #clock-cells = <0>;
 733                 compatible = "ti,gate-clock";
 734                 clocks = <&usbphy_32khz_clkmux>;
 735                 ti,bit-shift = <8>;
 736                 reg = <0x2a48>;
 737         };
 738
 739         usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
 740                 #clock-cells = <0>;
 741                 compatible = "ti,gate-clock";
 742                 clocks = <&dpll_per_clkdcoldo>;
 743                 ti,bit-shift = <8>;
 744                 reg = <0x8a60>;
 745         };
 746
 747         usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
 748                 #clock-cells = <0>;
 749                 compatible = "ti,gate-clock";
 750                 clocks = <&dpll_per_clkdcoldo>;
 751                 ti,bit-shift = <8>;
 752                 reg = <0x8a68>;
 753         };
 754 };