1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33XX SoC
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/am33xx.h>
11 #include <dt-bindings/clock/am3.h>
14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
49 compatible = "arm,cortex-a8";
50 enable-method = "ti,am3352";
54 operating-points-v2 = <&cpu0_opp_table>;
56 clocks = <&dpll_mpu_ck>;
59 clock-latency = <300000>; /* From omap-cpufreq driver */
60 cpu-idle-states = <&mpu_gate>;
65 compatible = "arm,idle-state";
66 entry-latency-us = <40>;
67 exit-latency-us = <90>;
68 min-residency-us = <300>;
74 cpu0_opp_table: opp-table {
75 compatible = "operating-points-v2-ti-cpu";
79 * The three following nodes are marked with opp-suspend
80 * because the can not be enabled simultaneously on a
84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <950000 931000 969000>;
86 opp-supported-hw = <0x06 0x0010>;
91 opp-hz = /bits/ 64 <275000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0x00FF>;
98 opp-hz = /bits/ 64 <300000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0020>;
105 opp-hz = /bits/ 64 <500000000>;
106 opp-microvolt = <1100000 1078000 1122000>;
107 opp-supported-hw = <0x01 0xFFFF>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <1100000 1078000 1122000>;
113 opp-supported-hw = <0x06 0x0040>;
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <1200000 1176000 1224000>;
119 opp-supported-hw = <0x01 0xFFFF>;
123 opp-hz = /bits/ 64 <720000000>;
124 opp-microvolt = <1200000 1176000 1224000>;
125 opp-supported-hw = <0x06 0x0080>;
129 opp-hz = /bits/ 64 <720000000>;
130 opp-microvolt = <1260000 1234800 1285200>;
131 opp-supported-hw = <0x01 0xFFFF>;
135 opp-hz = /bits/ 64 <800000000>;
136 opp-microvolt = <1260000 1234800 1285200>;
137 opp-supported-hw = <0x06 0x0100>;
140 oppnitro-1000000000 {
141 opp-hz = /bits/ 64 <1000000000>;
142 opp-microvolt = <1325000 1298500 1351500>;
143 opp-supported-hw = <0x04 0x0200>;
148 compatible = "arm,cortex-a8-pmu";
150 reg = <0x4b000000 0x1000000>;
151 ti,hwmods = "debugss";
155 * The soc node represents the soc top level view. It is used for IPs
156 * that are not memory mapped in the MPU view or for the MPU itself.
159 compatible = "ti,omap-infra";
161 compatible = "ti,omap3-mpu";
163 pm-sram = <&pm_sram_code
169 * XXX: Use a flat representation of the AM33XX interconnect.
170 * The real AM33XX interconnect network is quite complex. Since
171 * it will not bring real advantage to represent that in DT
172 * for the moment, just use a fake OCP bus entry to represent
173 * the whole bus hierarchy.
176 compatible = "simple-bus";
177 #address-cells = <1>;
180 ti,hwmods = "l3_main";
182 l4_wkup: l4_wkup@44c00000 {
183 wkup_m3: wkup_m3@100000 {
184 compatible = "ti,am3352-wkup-m3";
185 reg = <0x100000 0x4000>,
187 reg-names = "umem", "dmem";
188 ti,hwmods = "wkup_m3";
189 ti,pm-firmware = "am335x-pm-firmware.elf";
192 l4_per: interconnect@48000000 {
194 l4_fw: interconnect@47c00000 {
196 l4_fast: interconnect@4a000000 {
198 l4_mpuss: interconnect@4b140000 {
201 intc: interrupt-controller@48200000 {
202 compatible = "ti,am33xx-intc";
203 interrupt-controller;
204 #interrupt-cells = <1>;
205 reg = <0x48200000 0x1000>;
208 target-module@49000000 {
209 compatible = "ti,sysc-omap4", "ti,sysc";
210 reg = <0x49000000 0x4>;
212 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
214 #address-cells = <1>;
216 ranges = <0x0 0x49000000 0x10000>;
219 compatible = "ti,edma3-tpcc";
221 reg-names = "edma3_cc";
222 interrupts = <12 13 14>;
223 interrupt-names = "edma3_ccint", "edma3_mperr",
228 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
231 ti,edma-memcpy-channels = <20 21>;
235 target-module@49800000 {
236 compatible = "ti,sysc-omap4", "ti,sysc";
237 reg = <0x49800000 0x4>,
239 reg-names = "rev", "sysc";
240 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
241 ti,sysc-midle = <SYSC_IDLE_FORCE>;
242 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
244 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
246 #address-cells = <1>;
248 ranges = <0x0 0x49800000 0x100000>;
251 compatible = "ti,edma3-tptc";
254 interrupt-names = "edma3_tcerrint";
258 target-module@49900000 {
259 compatible = "ti,sysc-omap4", "ti,sysc";
260 reg = <0x49900000 0x4>,
262 reg-names = "rev", "sysc";
263 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
264 ti,sysc-midle = <SYSC_IDLE_FORCE>;
265 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
267 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
269 #address-cells = <1>;
271 ranges = <0x0 0x49900000 0x100000>;
274 compatible = "ti,edma3-tptc";
277 interrupt-names = "edma3_tcerrint";
281 target-module@49a00000 {
282 compatible = "ti,sysc-omap4", "ti,sysc";
283 reg = <0x49a00000 0x4>,
285 reg-names = "rev", "sysc";
286 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
287 ti,sysc-midle = <SYSC_IDLE_FORCE>;
288 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
290 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
292 #address-cells = <1>;
294 ranges = <0x0 0x49a00000 0x100000>;
297 compatible = "ti,edma3-tptc";
300 interrupt-names = "edma3_tcerrint";
304 target-module@47810000 {
305 compatible = "ti,sysc-omap2", "ti,sysc";
306 reg = <0x478102fc 0x4>,
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
311 SYSC_OMAP2_ENAWAKEUP |
312 SYSC_OMAP2_SOFTRESET |
313 SYSC_OMAP2_AUTOIDLE)>;
314 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
318 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
320 #address-cells = <1>;
322 ranges = <0x0 0x47810000 0x1000>;
325 compatible = "ti,am335-sdhci";
326 ti,needs-special-reset;
334 compatible = "ti,omap4-i2c";
335 #address-cells = <1>;
338 reg = <0x44e0b000 0x1000>;
344 compatible = "ti,omap4-i2c";
345 #address-cells = <1>;
348 reg = <0x4802a000 0x1000>;
354 compatible = "ti,omap4-i2c";
355 #address-cells = <1>;
358 reg = <0x4819c000 0x1000>;
364 compatible = "ti,omap4-hsmmc";
367 ti,needs-special-reset;
368 ti,needs-special-hs-handling;
369 dmas = <&edma_xbar 24 0 0
371 dma-names = "tx", "rx";
373 reg = <0x48060000 0x1000>;
378 compatible = "ti,omap4-hsmmc";
380 ti,needs-special-reset;
383 dma-names = "tx", "rx";
385 reg = <0x481d8000 0x1000>;
390 compatible = "ti,omap3-wdt";
391 ti,hwmods = "wd_timer2";
392 reg = <0x44e35000 0x1000>;
397 compatible = "ti,am33xx-usb";
398 reg = <0x47400000 0x1000>;
400 #address-cells = <1>;
402 ti,hwmods = "usb_otg_hs";
404 usb_ctrl_mod: control@44e10620 {
405 compatible = "ti,am335x-usb-ctrl-module";
406 reg = <0x44e10620 0x10
408 reg-names = "phy_ctrl", "wakeup";
411 usb0_phy: usb-phy@47401300 {
412 compatible = "ti,am335x-usb-phy";
413 reg = <0x47401300 0x100>;
415 ti,ctrl_mod = <&usb_ctrl_mod>;
420 compatible = "ti,musb-am33xx";
421 reg = <0x47401400 0x400
423 reg-names = "mc", "control";
426 interrupt-names = "mc";
428 mentor,multipoint = <1>;
429 mentor,num-eps = <16>;
430 mentor,ram-bits = <12>;
431 mentor,power = <500>;
434 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
435 &cppi41dma 2 0 &cppi41dma 3 0
436 &cppi41dma 4 0 &cppi41dma 5 0
437 &cppi41dma 6 0 &cppi41dma 7 0
438 &cppi41dma 8 0 &cppi41dma 9 0
439 &cppi41dma 10 0 &cppi41dma 11 0
440 &cppi41dma 12 0 &cppi41dma 13 0
441 &cppi41dma 14 0 &cppi41dma 0 1
442 &cppi41dma 1 1 &cppi41dma 2 1
443 &cppi41dma 3 1 &cppi41dma 4 1
444 &cppi41dma 5 1 &cppi41dma 6 1
445 &cppi41dma 7 1 &cppi41dma 8 1
446 &cppi41dma 9 1 &cppi41dma 10 1
447 &cppi41dma 11 1 &cppi41dma 12 1
448 &cppi41dma 13 1 &cppi41dma 14 1>;
450 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
451 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
453 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
454 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
458 usb1_phy: usb-phy@47401b00 {
459 compatible = "ti,am335x-usb-phy";
460 reg = <0x47401b00 0x100>;
462 ti,ctrl_mod = <&usb_ctrl_mod>;
467 compatible = "ti,musb-am33xx";
468 reg = <0x47401c00 0x400
470 reg-names = "mc", "control";
472 interrupt-names = "mc";
474 mentor,multipoint = <1>;
475 mentor,num-eps = <16>;
476 mentor,ram-bits = <12>;
477 mentor,power = <500>;
480 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
481 &cppi41dma 17 0 &cppi41dma 18 0
482 &cppi41dma 19 0 &cppi41dma 20 0
483 &cppi41dma 21 0 &cppi41dma 22 0
484 &cppi41dma 23 0 &cppi41dma 24 0
485 &cppi41dma 25 0 &cppi41dma 26 0
486 &cppi41dma 27 0 &cppi41dma 28 0
487 &cppi41dma 29 0 &cppi41dma 15 1
488 &cppi41dma 16 1 &cppi41dma 17 1
489 &cppi41dma 18 1 &cppi41dma 19 1
490 &cppi41dma 20 1 &cppi41dma 21 1
491 &cppi41dma 22 1 &cppi41dma 23 1
492 &cppi41dma 24 1 &cppi41dma 25 1
493 &cppi41dma 26 1 &cppi41dma 27 1
494 &cppi41dma 28 1 &cppi41dma 29 1>;
496 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
497 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
499 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
500 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
504 cppi41dma: dma-controller@2000 {
505 compatible = "ti,am3359-cppi41";
506 reg = <0x0000 0x1000>,
510 reg-names = "glue", "controller", "scheduler", "queuemgr";
512 interrupt-names = "glue";
514 #dma-channels = <30>;
515 #dma-requests = <256>;
519 mac: ethernet@4a100000 {
520 compatible = "ti,am335x-cpsw","ti,cpsw";
521 ti,hwmods = "cpgmac0";
522 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
523 clock-names = "fck", "cpts";
524 cpdma_channels = <8>;
525 ale_entries = <1024>;
526 bd_ram_size = <0x2000>;
527 mac_control = <0x20>;
530 cpts_clock_mult = <0x80000000>;
531 cpts_clock_shift = <29>;
532 reg = <0x4a100000 0x800
534 #address-cells = <1>;
542 interrupts = <40 41 42 43>;
544 syscon = <&scm_conf>;
547 davinci_mdio: mdio@4a101000 {
548 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
549 #address-cells = <1>;
551 ti,hwmods = "davinci_mdio";
552 bus_freq = <1000000>;
553 reg = <0x4a101000 0x100>;
557 cpsw_emac0: slave@4a100200 {
558 /* Filled in by U-Boot */
559 mac-address = [ 00 00 00 00 00 00 ];
562 cpsw_emac1: slave@4a100300 {
563 /* Filled in by U-Boot */
564 mac-address = [ 00 00 00 00 00 00 ];
567 phy_sel: cpsw-phy-sel@44e10650 {
568 compatible = "ti,am3352-cpsw-phy-sel";
569 reg= <0x44e10650 0x4>;
570 reg-names = "gmii-sel";
574 ocmcram: sram@40300000 {
575 compatible = "mmio-sram";
576 reg = <0x40300000 0x10000>; /* 64k */
577 ranges = <0x0 0x40300000 0x10000>;
578 #address-cells = <1>;
581 pm_sram_code: pm-code-sram@0 {
582 compatible = "ti,sram";
587 pm_sram_data: pm-data-sram@1000 {
588 compatible = "ti,sram";
589 reg = <0x1000 0x1000>;
594 emif: emif@4c000000 {
595 compatible = "ti,emif-am3352";
596 reg = <0x4c000000 0x1000000>;
599 sram = <&pm_sram_code
604 gpmc: gpmc@50000000 {
605 compatible = "ti,am3352-gpmc";
608 reg = <0x50000000 0x2000>;
613 gpmc,num-waitpins = <2>;
614 #address-cells = <2>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
623 sham_target: target-module@53100000 {
624 compatible = "ti,sysc-omap3-sham", "ti,sysc";
625 reg = <0x53100100 0x4>,
628 reg-names = "rev", "sysc", "syss";
629 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
630 SYSC_OMAP2_AUTOIDLE)>;
631 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
635 /* Domains (P, C): per_pwrdm, l3_clkdm */
636 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
638 #address-cells = <1>;
640 ranges = <0x0 0x53100000 0x1000>;
643 compatible = "ti,omap4-sham";
651 aes_target: target-module@53500000 {
652 compatible = "ti,sysc-omap2", "ti,sysc";
653 reg = <0x53500080 0x4>,
656 reg-names = "rev", "sysc", "syss";
657 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
658 SYSC_OMAP2_AUTOIDLE)>;
659 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
662 <SYSC_IDLE_SMART_WKUP>;
664 /* Domains (P, C): per_pwrdm, l3_clkdm */
665 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
667 #address-cells = <1>;
669 ranges = <0x0 0x53500000 0x1000>;
672 compatible = "ti,omap4-aes";
677 dma-names = "tx", "rx";
681 target-module@56000000 {
682 compatible = "ti,sysc-omap4", "ti,sysc";
683 reg = <0x5600fe00 0x4>,
685 reg-names = "rev", "sysc";
686 ti,sysc-midle = <SYSC_IDLE_FORCE>,
689 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
692 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
694 resets = <&prm_gfx 0>;
695 reset-names = "rstctrl";
696 #address-cells = <1>;
698 ranges = <0 0x56000000 0x1000000>;
701 * Closed source PowerVR driver, no child device
702 * binding or driver in mainline
708 #include "am33xx-l4.dtsi"
709 #include "am33xx-clocks.dtsi"
713 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
719 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
724 prm_device: prm@f00 {
725 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
731 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
732 reg = <0x1100 0x100>;