arch/arm/dts/am335x-guardian.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   4  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
   5  */
   6 /dts-v1/;
   7
   8 #include "am33xx.dtsi"
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         model = "Bosch AM335x Guardian";
  14         compatible = "bosch,am335x-guardian", "ti,am33xx";
  15
  16         chosen {
  17                 stdout-path = &uart0;
  18                 tick-timer = &timer2;
  19         };
  20
  21         cpus {
  22                 cpu@0 {
  23                         cpu0-supply = <&dcdc2_reg>;
  24                 };
  25         };
  26
  27         memory@80000000 {
  28                 device_type = "memory";
  29                 reg = <0x80000000 0x10000000>; /* 256 MB */
  30         };
  31
  32         gpio_keys {
  33                 compatible = "gpio-keys";
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&guardian_button_pins>;
  36
  37                 select-button {
  38                         label = "guardian-select-button";
  39                         linux,code = <KEY_5>;
  40                         gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
  41                         wakeup-source;
  42                 };
  43
  44                 power-button {
  45                         label = "guardian-power-button";
  46                         linux,code = <KEY_POWER>;
  47                         gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
  48                         wakeup-source;
  49                 };
  50         };
  51
  52         leds {
  53                 compatible = "gpio-leds";
  54                 pinctrl-names = "default";
  55                 pinctrl-0 = <&guardian_led_pins>;
  56
  57                 life-led {
  58                         label = "guardian:life-led";
  59                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  60                         linux,default-trigger = "heartbeat";
  61                         default-state = "on";
  62                 };
  63         };
  64
  65         panel {
  66                 compatible = "ti,tilcdc,panel";
  67                 pinctrl-names = "default", "sleep";
  68                 pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>;
  69                 pinctrl-1 = <&lcd_pins_sleep>;
  70
  71                 display-timings {
  72                         320x240 {
  73                                 hactive         = <320>;
  74                                 vactive         = <240>;
  75                                 hback-porch     = <68>;
  76                                 hfront-porch    = <20>;
  77                                 hsync-len       = <1>;
  78                                 vback-porch     = <18>;
  79                                 vfront-porch    = <4>;
  80                                 vsync-len       = <1>;
  81                                 clock-frequency = <9000000>;
  82                                 hsync-active    = <0>;
  83                                 vsync-active    = <0>;
  84                         };
  85                 };
  86                 panel-info {
  87                         ac-bias           = <255>;
  88                         ac-bias-intrpt    = <0>;
  89                         dma-burst-sz      = <16>;
  90                         bpp               = <16>;
  91                         bus-width         = <16>;
  92                         fdd               = <0x80>;
  93                         sync-edge         = <0>;
  94                         sync-ctrl         = <1>;
  95                         raster-order      = <0>;
  96                         fifo-th           = <0>;
  97                 };
  98
  99         };
 100
 101         pwm7: dmtimer-pwm {
 102                 compatible = "ti,omap-dmtimer-pwm";
 103                 ti,timers = <&timer7>;
 104                 pinctrl-names = "default";
 105                 pinctrl-0 = <&dmtimer7_pins>;
 106         };
 107
 108         vmmcsd_fixed: regulator-3v3 {
 109                 compatible = "regulator-fixed";
 110                 regulator-name = "vmmcsd_fixed";
 111                 regulator-min-microvolt = <3300000>;
 112                 regulator-max-microvolt = <3300000>;
 113         };
 114 };
 115
 116 &cppi41dma  {
 117         status = "okay";
 118 };
 119
 120 &elm {
 121         status = "okay";
 122 };
 123
 124 &gpmc {
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&nandflash_pins>;
 127         ranges = <0 0 0x08000000 0x1000000>;  /* CS0: 16MB for NAND */
 128         status = "okay";
 129
 130         nand@0,0 {
 131                 compatible = "ti,omap2-nand";
 132                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 133                 interrupt-parent = <&gpmc>;
 134                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 135                              <1 IRQ_TYPE_NONE>; /* termcount */
 136                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 137                 ti,nand-ecc-opt = "bch16";
 138                 ti,elm-id = <&elm>;
 139                 nand-bus-width = <8>;
 140                 gpmc,device-width = <1>;
 141                 gpmc,sync-clk-ps = <0>;
 142                 gpmc,cs-on-ns = <0>;
 143                 gpmc,cs-rd-off-ns = <30>;
 144                 gpmc,cs-wr-off-ns = <30>;
 145                 gpmc,adv-on-ns = <0>;
 146                 gpmc,adv-rd-off-ns = <30>;
 147                 gpmc,adv-wr-off-ns = <30>;
 148                 gpmc,we-on-ns = <0>;
 149                 gpmc,we-off-ns = <15>;
 150                 gpmc,oe-on-ns = <1>;
 151                 gpmc,oe-off-ns = <15>;
 152                 gpmc,access-ns = <30>;
 153                 gpmc,rd-cycle-ns = <30>;
 154                 gpmc,wr-cycle-ns = <30>;
 155                 gpmc,wait-on-read = "true";
 156                 gpmc,wait-on-write = "true";
 157                 gpmc,bus-turnaround-ns = <0>;
 158                 gpmc,cycle2cycle-delay-ns = <0>;
 159                 gpmc,clk-activation-ns = <0>;
 160                 gpmc,wait-monitoring-ns = <0>;
 161                 gpmc,wr-access-ns = <0>;
 162                 gpmc,wr-data-mux-bus-ns = <0>;
 163
 164                 /*
 165                  * MTD partition table
 166                  *
 167                  * All SPL-* partitions are sized to minimal length which can
 168                  * be independently programmable. For NAND flash this is equal
 169                  * to size of erase-block.
 170                  */
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173
 174                 partition@0 {
 175                         label = "SPL";
 176                         reg = <0x0 0x40000>;
 177                 };
 178
 179                 partition@1 {
 180                         label = "SPL.backup1";
 181                         reg = <0x40000  0x40000>;
 182                 };
 183
 184                 partition@2 {
 185                         label = "SPL.backup2";
 186                         reg = <0x80000  0x40000>;
 187                 };
 188
 189                 partition@3 {
 190                         label = "SPL.backup3";
 191                         reg = <0xc0000  0x40000>;
 192                 };
 193
 194                 partition@4 {
 195                         label = "u-boot";
 196                         reg = <0x100000 0x100000>;
 197                 };
 198
 199                 partition@5 {
 200                         label = "u-boot.backup1";
 201                         reg = <0x200000 0x100000>;
 202                 };
 203
 204                 partition@6 {
 205                         label = "u-boot-2";
 206                         reg = <0x300000 0x100000>;
 207                 };
 208
 209                 partition@7 {
 210                         label = "u-boot-2.backup1";
 211                         reg = <0x400000 0x100000>;
 212                 };
 213
 214                 partition@8 {
 215                         label = "u-boot-env";
 216                         reg = <0x500000 0x40000>;
 217                 };
 218
 219                 partition@9 {
 220                         label = "u-boot-env.backup1";
 221                         reg = <0x540000 0x40000>;
 222                 };
 223
 224                 partition@10 {
 225                         label = "splash-screen";
 226                         reg = <0x580000 0x40000>;
 227                 };
 228
 229                 partition@11 {
 230                         label = "UBI";
 231                         reg = <0x5c0000 0x1fa40000>;
 232                 };
 233         };
 234 };
 235
 236 &i2c0 {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&i2c0_pins>;
 239         clock-frequency = <400000>;
 240         status = "okay";
 241
 242         tps: tps@24 {
 243                 reg = <0x24>;
 244         };
 245 };
 246
 247 &lcdc {
 248         blue-and-red-wiring = "crossed";
 249         status = "okay";
 250
 251         port {
 252                 lcdc_0: endpoint@0 {
 253                         remote-endpoint = <0>;
 254                 };
 255         };
 256 };
 257
 258 &mmc1 {
 259         bus-width = <0x4>;
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&mmc1_pins>;
 262         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 263         vmmc-supply = <&vmmcsd_fixed>;
 264         status = "okay";
 265 };
 266
 267 &rtc {
 268         clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 269         clock-names = "ext-clk", "int-clk";
 270         system-power-controller;
 271 };
 272
 273 &spi0 {
 274         ti,pindir-d0-out-d1-in;
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&spi0_pins>;
 277         status = "okay";
 278 };
 279
 280 /include/ "tps65217.dtsi"
 281
 282 &tps {
 283         ti,pmic-shutdown-controller;
 284         interrupt-parent = <&intc>;
 285         interrupts = <7>; /* NMI */
 286
 287         backlight {
 288                 isel = <1>;  /* 1 - ISET1, 2 ISET2 */
 289                 fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
 290                 default-brightness = <100>;
 291         };
 292
 293         regulators {
 294                 dcdc1_reg: regulator@0 {
 295                         regulator-name = "vdds_dpr";
 296                         regulator-always-on;
 297                 };
 298
 299                 dcdc2_reg: regulator@1 {
 300                         regulator-name = "vdd_mpu";
 301                         regulator-min-microvolt = <925000>;
 302                         regulator-max-microvolt = <1351500>;
 303                         regulator-boot-on;
 304                         regulator-always-on;
 305                 };
 306
 307                 dcdc3_reg: regulator@2 {
 308                         regulator-name = "vdd_core";
 309                         regulator-min-microvolt = <925000>;
 310                         regulator-max-microvolt = <1150000>;
 311                         regulator-boot-on;
 312                         regulator-always-on;
 313                 };
 314
 315                 ldo1_reg: regulator@3 {
 316                         regulator-name = "vio,vrtc,vdds";
 317                         regulator-always-on;
 318                 };
 319
 320                 ldo2_reg: regulator@4 {
 321                         regulator-name = "vdd_3v3aux";
 322                         regulator-always-on;
 323                 };
 324
 325                 ldo3_reg: regulator@5 {
 326                         regulator-name = "vdd_1v8";
 327                         regulator-min-microvolt = <1800000>;
 328                         regulator-max-microvolt = <1800000>;
 329                         regulator-always-on;
 330                 };
 331
 332                 ldo4_reg: regulator@6 {
 333                         regulator-name = "vdd_3v3a";
 334                         regulator-always-on;
 335                 };
 336         };
 337 };
 338
 339 &tscadc {
 340         status = "okay";
 341
 342         adc {
 343                 ti,adc-channels = <0 1 2 3 4 5 6>;
 344         };
 345 };
 346
 347 &uart0 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&uart0_pins>;
 350         status = "okay";
 351 };
 352
 353 &uart2 {
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&uart2_pins>;
 356         status = "okay";
 357 };
 358
 359 &usb {
 360         status = "okay";
 361 };
 362
 363 &usb_ctrl_mod {
 364         status = "okay";
 365 };
 366
 367 &usb0 {
 368         dr_mode = "peripheral";
 369         status = "okay";
 370 };
 371
 372 &usb0_phy {
 373         status = "okay";
 374 };
 375
 376 &usb1 {
 377         dr_mode = "host";
 378         status = "okay";
 379 };
 380
 381 &usb1_phy {
 382         status = "okay";
 383 };
 384
 385 &am33xx_pinmux {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&clkout2_pin &guardian_interface_pins>;
 388
 389         clkout2_pin: pinmux_clkout2_pin {
 390                 pinctrl-single,pins = <
 391                         AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
 392                 >;
 393         };
 394
 395         dmtimer7_pins: pinmux_dmtimer7_pins {
 396                 pinctrl-single,pins = <
 397                         AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE5)
 398                 >;
 399         };
 400
 401         guardian_button_pins: pinmux_gpio_keys_pins {
 402                 pinctrl-single,pins = <
 403                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE7)
 404                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT, MUX_MODE7)
 405                 >;
 406         };
 407
 408         guardian_interface_pins: pinmux_guardian_interface_pins {
 409                 pinctrl-single,pins = <
 410                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLUP, MUX_MODE7)
 411                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 412                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 413                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE7)
 414                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE7)
 415                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE7)
 416                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 417                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 418                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT, MUX_MODE7)
 419                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 420                 >;
 421         };
 422
 423         i2c0_pins: pinmux_i2c0_pins {
 424                 pinctrl-single,pins = <
 425                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
 426                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 427                 >;
 428         };
 429
 430         lcd_disen_pins: pinmux_lcd_disen_pins {
 431                 pinctrl-single,pins = <
 432                         AM33XX_PADCONF
 433                         (AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW, MUX_MODE7)
 434                 >;
 435         };
 436
 437         lcd_pins_default: pinmux_lcd_pins_default {
 438                 pinctrl-single,pins = <
 439                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 440                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 441                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 442                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 443                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 444                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 445                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 446                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
 447                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 448                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 449                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 450                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 451                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 452                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 453                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 454                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 455                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 456                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 457                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 458                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 459                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 460                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 461                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 462                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 463                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 464                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 465                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 466                         AM33XX_PADCONF
 467                         (AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
 468                 >;
 469         };
 470
 471         lcd_pins_sleep: pinmux_lcd_pins_sleep {
 472                 pinctrl-single,pins = <
 473                         AM33XX_PADCONF
 474                         (AM335X_PIN_LCD_DATA0, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 475                         AM33XX_PADCONF
 476                         (AM335X_PIN_LCD_DATA1, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 477                         AM33XX_PADCONF
 478                         (AM335X_PIN_LCD_DATA2, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 479                         AM33XX_PADCONF
 480                         (AM335X_PIN_LCD_DATA3, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 481                         AM33XX_PADCONF
 482                         (AM335X_PIN_LCD_DATA4, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 483                         AM33XX_PADCONF
 484                         (AM335X_PIN_LCD_DATA5, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 485                         AM33XX_PADCONF
 486                         (AM335X_PIN_LCD_DATA6, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 487                         AM33XX_PADCONF
 488                         (AM335X_PIN_LCD_DATA7, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 489                         AM33XX_PADCONF
 490                         (AM335X_PIN_LCD_DATA8, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 491                         AM33XX_PADCONF
 492                         (AM335X_PIN_LCD_DATA9, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 493                         AM33XX_PADCONF
 494                         (AM335X_PIN_LCD_DATA10, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 495                         AM33XX_PADCONF
 496                         (AM335X_PIN_LCD_DATA11, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 497                         AM33XX_PADCONF
 498                         (AM335X_PIN_LCD_DATA12, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 499                         AM33XX_PADCONF
 500                         (AM335X_PIN_LCD_DATA13, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 501                         AM33XX_PADCONF
 502                         (AM335X_PIN_LCD_DATA14, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 503                         AM33XX_PADCONF
 504                         (AM335X_PIN_LCD_DATA15, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
 505                         AM33XX_PADCONF
 506                         (AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
 507                         AM33XX_PADCONF
 508                         (AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
 509                         AM33XX_PADCONF
 510                         (AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
 511                         AM33XX_PADCONF
 512                         (AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
 513                 >;
 514         };
 515
 516         guardian_led_pins: pinmux_leds_pins {
 517                 pinctrl-single,pins = <
 518                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_OUTPUT, MUX_MODE7)
 519                 >;
 520         };
 521
 522         mmc1_pins: pinmux_mmc1_pins {
 523                 pinctrl-single,pins = <
 524                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
 525                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
 526                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
 527                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
 528                         AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 529                         AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
 530                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)
 531                 >;
 532         };
 533
 534         spi0_pins: pinmux_spi0_pins {
 535                 pinctrl-single,pins = <
 536                         AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 537                         AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0)
 538                         AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
 539                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT_PULLUP, MUX_MODE0)
 540                 >;
 541         };
 542
 543         uart0_pins: pinmux_uart0_pins {
 544                 pinctrl-single,pins = <
 545                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
 546                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 547                 >;
 548         };
 549
 550         uart2_pins: pinmux_uart2_pins {
 551                 pinctrl-single,pins = <
 552                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)
 553                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
 554                 >;
 555         };
 556
 557         nandflash_pins: pinmux_nandflash_pins {
 558                 pinctrl-single,pins = <
 559                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT, MUX_MODE0)
 560                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT, MUX_MODE0)
 561                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT, MUX_MODE0)
 562                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT, MUX_MODE0)
 563                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT, MUX_MODE0)
 564                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT, MUX_MODE0)
 565                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT, MUX_MODE0)
 566                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT, MUX_MODE0)
 567                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE0)
 568                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT, MUX_MODE0)
 569                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
 570                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
 571                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
 572                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
 573                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
 574                 >;
 575         };
 576 };