1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
4 * Author: Rostislav Lisovy <lisovy@jablotron.cz>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 model = "Grinn AM335x ChiliSOM";
11 compatible = "grinn,am335x-chilisom", "ti,am33xx";
15 cpu0-supply = <&dcdc2_reg>;
20 device_type = "memory";
21 reg = <0x80000000 0x20000000>; /* 512 MB */
26 pinctrl-names = "default";
28 i2c0_pins: pinmux_i2c0_pins {
29 pinctrl-single,pins = <
30 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
31 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
35 nandflash_pins: nandflash_pins {
36 pinctrl-single,pins = <
37 AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
38 AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
39 AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
40 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
41 AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
42 AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
43 AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
44 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
46 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
47 AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
48 AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
49 AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
50 AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
51 AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
57 pinctrl-names = "default";
58 pinctrl-0 = <&i2c0_pins>;
61 clock-frequency = <400000>;
69 /include/ "tps65217.dtsi"
73 dcdc1_reg: regulator@0 {
74 regulator-name = "vdds_dpr";
78 dcdc2_reg: regulator@1 {
79 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
80 regulator-name = "vdd_mpu";
81 regulator-min-microvolt = <925000>;
82 regulator-max-microvolt = <1325000>;
87 dcdc3_reg: regulator@2 {
88 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
89 regulator-name = "vdd_core";
90 regulator-min-microvolt = <925000>;
91 regulator-max-microvolt = <1150000>;
96 ldo1_reg: regulator@3 {
97 regulator-name = "vio,vrtc,vdds";
102 ldo2_reg: regulator@4 {
103 regulator-name = "vdd_3v3aux";
108 ldo3_reg: regulator@5 {
109 regulator-name = "vdd_1v8";
114 ldo4_reg: regulator@6 {
115 regulator-name = "vdd_3v3d";
123 system-power-controller;
125 pinctrl-0 = <&ext_wakeup>;
126 pinctrl-names = "default";
128 ext_wakeup: ext-wakeup {
129 pins = "ext_wakeup0";
141 pinctrl-names = "default";
142 pinctrl-0 = <&nandflash_pins>;
143 ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
145 compatible = "ti,omap2-nand";
146 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
147 interrupt-parent = <&gpmc>;
148 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
149 <1 IRQ_TYPE_NONE>; /* termcount */
150 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
151 ti,nand-ecc-opt = "bch8";
153 nand-bus-width = <8>;
154 gpmc,device-width = <1>;
155 gpmc,sync-clk-ps = <0>;
157 gpmc,cs-rd-off-ns = <44>;
158 gpmc,cs-wr-off-ns = <44>;
159 gpmc,adv-on-ns = <6>;
160 gpmc,adv-rd-off-ns = <34>;
161 gpmc,adv-wr-off-ns = <44>;
163 gpmc,we-off-ns = <40>;
165 gpmc,oe-off-ns = <54>;
166 gpmc,access-ns = <64>;
167 gpmc,rd-cycle-ns = <82>;
168 gpmc,wr-cycle-ns = <82>;
169 gpmc,bus-turnaround-ns = <0>;
170 gpmc,cycle2cycle-delay-ns = <0>;
171 gpmc,clk-activation-ns = <0>;
172 gpmc,wr-access-ns = <40>;
173 gpmc,wr-data-mux-bus-ns = <0>;