arch/arm/dts/ac5-98dx25xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree For AC5.
   4  *
   5  * Copyright (C) 2021 Marvell
   6  * Copyright (C) 2022 Allied Telesis Labs
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         model = "Marvell AC5 SoC";
  14         compatible = "marvell,ac5";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32                 };
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a55";
  37                         reg = <0x0 0x0>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&l2>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a55";
  45                         reg = <0x0 0x100>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                 };
  49
  50                 l2: l2-cache {
  51                         compatible = "cache";
  52                 };
  53         };
  54
  55         psci {
  56                 compatible = "arm,psci-0.2";
  57                 method = "smc";
  58         };
  59
  60         timer {
  61                 compatible = "arm,armv8-timer";
  62                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
  63                              <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
  64                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
  65                              <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  66         };
  67
  68         pmu {
  69                 compatible = "arm,armv8-pmuv3";
  70                 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
  71         };
  72
  73         soc {
  74                 compatible = "simple-bus";
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77                 ranges;
  78                 dma-ranges;
  79
  80                 internal-regs@7f000000 {
  81                         #address-cells = <1>;
  82                         #size-cells = <1>;
  83                         compatible = "simple-bus";
  84                         /* 16M internal register @ 0x7f00_0000 */
  85                         ranges = <0x0 0x0 0x7f000000 0x1000000>;
  86                         dma-coherent;
  87
  88                         uart0: serial@12000 {
  89                                 compatible = "snps,dw-apb-uart";
  90                                 reg = <0x12000 0x100>;
  91                                 reg-shift = <2>;
  92                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  93                                 reg-io-width = <1>;
  94                                 clocks = <&cnm_clock>;
  95                                 status = "okay";
  96                         };
  97
  98                         uart1: serial@12100 {
  99                                 compatible = "snps,dw-apb-uart";
 100                                 reg = <0x12100 0x100>;
 101                                 reg-shift = <2>;
 102                                 reg-io-width = <1>;
 103                                 clocks = <&cnm_clock>;
 104                                 status = "disabled";
 105                         };
 106
 107                         uart2: serial@12200 {
 108                                 compatible = "snps,dw-apb-uart";
 109                                 reg = <0x12200 0x100>;
 110                                 reg-shift = <2>;
 111                                 reg-io-width = <1>;
 112                                 clocks = <&cnm_clock>;
 113                                 status = "disabled";
 114                         };
 115
 116                         uart3: serial@12300 {
 117                                 compatible = "snps,dw-apb-uart";
 118                                 reg = <0x12300 0x100>;
 119                                 reg-shift = <2>;
 120                                 reg-io-width = <1>;
 121                                 clocks = <&cnm_clock>;
 122                                 status = "disabled";
 123                         };
 124
 125                         mdio: mdio@22004 {
 126                                 #address-cells = <1>;
 127                                 #size-cells = <0>;
 128                                 compatible = "marvell,orion-mdio";
 129                                 reg = <0x22004 0x4>;
 130                                 clocks = <&cnm_clock>;
 131                         };
 132
 133                         i2c0: i2c@11000 {
 134                                 compatible = "marvell,mv78230-i2c";
 135                                 reg = <0x11000 0x20>;
 136                                 #address-cells = <1>;
 137                                 #size-cells = <0>;
 138
 139                                 clocks = <&cnm_clock>;
 140                                 clock-names = "core";
 141                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 142                                 clock-frequency=<100000>;
 143                                 status = "disabled";
 144                         };
 145
 146                         i2c1: i2c@11100 {
 147                                 compatible = "marvell,mv78230-i2c";
 148                                 reg = <0x11100 0x20>;
 149                                 #address-cells = <1>;
 150                                 #size-cells = <0>;
 151
 152                                 clocks = <&cnm_clock>;
 153                                 clock-names = "core";
 154                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 155                                 clock-frequency=<100000>;
 156                                 status = "disabled";
 157                         };
 158
 159                         gpio0: gpio@18100 {
 160                                 compatible = "marvell,orion-gpio";
 161                                 reg = <0x18100 0x40>;
 162                                 ngpios = <32>;
 163                                 gpio-controller;
 164                                 #gpio-cells = <2>;
 165                                 status = "okay";
 166                         };
 167
 168                         gpio1: gpio@18140 {
 169                                 reg = <0x18140 0x40>;
 170                                 compatible = "marvell,orion-gpio";
 171                                 ngpios = <14>;
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                                 status = "okay";
 175                         };
 176                 };
 177
 178                 /*
 179                  * Dedicated section for devices behind 32bit controllers so we
 180                  * can configure specific DMA mapping for them
 181                  */
 182                 behind-32bit-controller@7f000000 {
 183                         compatible = "simple-bus";
 184                         #address-cells = <0x2>;
 185                         #size-cells = <0x2>;
 186                         ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
 187                         /* Host phy ram starts at 0x200M */
 188                         dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
 189                         dma-coherent;
 190
 191                         eth0: ethernet@20000 {
 192                                 compatible = "marvell,armada-ac5-neta";
 193                                 reg = <0x0 0x20000 0x0 0x4000>;
 194                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 195                                 clocks = <&cnm_clock>;
 196                                 phy-mode = "sgmii";
 197                                 status = "disabled";
 198                         };
 199
 200                         eth1: ethernet@24000 {
 201                                 compatible = "marvell,armada-ac5-neta";
 202                                 reg = <0x0 0x24000 0x0 0x4000>;
 203                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 204                                 clocks = <&cnm_clock>;
 205                                 phy-mode = "sgmii";
 206                                 status = "disabled";
 207                         };
 208
 209                         usb0: usb@80000 {
 210                                 compatible = "marvell,ac5-ehci";
 211                                 reg = <0x0 0x80000 0x0 0x500>;
 212                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 213                                 status = "disabled";
 214                         };
 215
 216                         usb1: usb@a0000 {
 217                                 compatible = "marvell,ac5-ehci";
 218                                 reg = <0x0 0xa0000 0x0 0x500>;
 219                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 220                                 status = "disabled";
 221                         };
 222                 };
 223
 224                 pinctrl0: pinctrl@80020100 {
 225                         compatible = "marvell,mvebu-pinctrl";
 226                         reg = <0 0x80020100 0 0x20>;
 227                         pin-count = <46>;
 228                         max-func = <0xf>;
 229                         status = "okay";
 230                 };
 231
 232                 spi0: spi@805a0000 {
 233                         compatible = "marvell,armada-3700-spi";
 234                         reg = <0x0 0x805a0000 0x0 0x50>;
 235                         #address-cells = <0x1>;
 236                         #size-cells = <0x0>;
 237                         clocks = <&spi_clock>;
 238                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 239                         num-cs = <1>;
 240                         status = "disabled";
 241                 };
 242
 243                 spi1: spi@805a8000 {
 244                         compatible = "marvell,armada-3700-spi";
 245                         reg = <0x0 0x805a8000 0x0 0x50>;
 246                         #address-cells = <0x1>;
 247                         #size-cells = <0x0>;
 248                         clocks = <&spi_clock>;
 249                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 250                         num-cs = <1>;
 251                         status = "disabled";
 252                 };
 253
 254                 gic: interrupt-controller@80600000 {
 255                         compatible = "arm,gic-v3";
 256                         #interrupt-cells = <3>;
 257                         interrupt-controller;
 258                         reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
 259                               <0x0 0x80660000 0x0 0x40000>; /* GICR */
 260                         interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 261                 };
 262         };
 263
 264         clocks {
 265                 cnm_clock: cnm-clock {
 266                         compatible = "fixed-clock";
 267                         #clock-cells = <0>;
 268                         clock-frequency = <328000000>;
 269                 };
 270
 271                 spi_clock: spi-clock {
 272                         compatible = "fixed-clock";
 273                         #clock-cells = <0>;
 274                         clock-frequency = <200000000>;
 275                 };
 276         };
 277 };