2 * Startup Code for S3C44B0 CPU-core
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30 #include <asm-offsets.h>
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
49 .balignl 16,0xdeadbeef
53 *************************************************************************
55 * Startup Code (reset vector)
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
60 * jump to second stage
62 *************************************************************************
67 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
68 .word CONFIG_SPL_TEXT_BASE
70 .word CONFIG_SYS_TEXT_BASE
74 * These are defined in the board-specific linker script.
75 * Subtracting _start from them lets the linker put their
76 * relative position in the executable instead of leaving
81 .word __bss_start - _start
85 .word __bss_end - _start
92 /* IRQ stack memory (calculated at run-time) */
93 .globl IRQ_STACK_START
97 /* IRQ stack memory (calculated at run-time) */
98 .globl FIQ_STACK_START
103 /* IRQ stack memory (calculated at run-time) + 8 bytes */
104 .globl IRQ_STACK_START_IN
109 * the actual reset code
114 * set the cpu to SVC32 mode
122 * we do sys-critical inits only at reboot,
123 * not when booting from ram!
125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
128 * before relocating, we have to setup RAM timing
129 * because memory timing is board-dependend, you will
130 * find a lowlevel_init.S in your board directory.
137 /*------------------------------------------------------------------------------*/
139 #ifndef CONFIG_SPL_BUILD
141 * void relocate_code(addr_moni)
143 * This function relocates the monitor code.
147 mov r6, r0 /* save addr of destination */
150 subs r9, r6, r0 /* r9 <- relocation offset */
151 beq relocate_done /* skip relocation */
152 mov r1, r6 /* r1 <- scratch for copy_loop */
153 ldr r3, _image_copy_end_ofs
154 add r2, r0, r3 /* r2 <- source end address */
157 ldmia r0!, {r10-r11} /* copy from source address [r0] */
158 stmia r1!, {r10-r11} /* copy to target address [r1] */
159 cmp r0, r2 /* until source end address [r2] */
163 * fix .rel.dyn relocations
165 ldr r0, _TEXT_BASE /* r0 <- Text base */
166 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
167 add r10, r10, r0 /* r10 <- sym table in FLASH */
168 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
169 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
170 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
171 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
173 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
174 add r0, r0, r9 /* r0 <- location to fix up in RAM */
177 cmp r7, #23 /* relative fixup? */
179 cmp r7, #2 /* absolute fixup? */
181 /* ignore unknown type of fixup */
184 /* absolute fix: set location to (offset) symbol value */
185 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
186 add r1, r10, r1 /* r1 <- address of symbol in table */
187 ldr r1, [r1, #4] /* r1 <- symbol value */
188 add r1, r1, r9 /* r1 <- relocated sym addr */
191 /* relative fix: increase location by offset */
196 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
205 .word __image_copy_end - _start
207 .word __rel_dyn_start - _start
209 .word __rel_dyn_end - _start
211 .word __dynsym_start - _start
215 .globl c_runtime_cpu_setup
221 *************************************************************************
223 * CPU_init_critical registers
225 * setup important registers
226 * setup memory timing
228 *************************************************************************
231 #define INTCON (0x01c00000+0x200000)
232 #define INTMSK (0x01c00000+0x20000c)
233 #define LOCKTIME (0x01c00000+0x18000c)
234 #define PLLCON (0x01c00000+0x180000)
235 #define CLKCON (0x01c00000+0x180004)
236 #define WTCON (0x01c00000+0x130000)
238 /* disable watch dog */
244 * mask all IRQs by clearing all bits in the INTMRs
254 /* Set Clock Control Register */
261 #if CONFIG_S3C44B0_CLOCK_SPEED==66
262 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
263 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
264 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
266 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
278 /*************************************************/
279 /* interrupt vectors */
280 /*************************************************/
283 b undefined_instruction
291 /*************************************************/
293 undefined_instruction:
310 /* we *should* never reach this */