2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/pxa-regs.h>
37 ldr pc, _undefined_instruction
38 ldr pc, _software_interrupt
39 ldr pc, _prefetch_abort
45 _undefined_instruction: .word undefined_instruction
46 _software_interrupt: .word software_interrupt
47 _prefetch_abort: .word prefetch_abort
48 _data_abort: .word data_abort
49 _not_used: .word not_used
53 .balignl 16,0xdeadbeef
57 * Startup Code (reset vector)
59 * do important init only if we don't start from RAM!
60 * - relocate armboot to RAM
62 * - jump to second stage
73 * These are defined in the board-specific linker script.
84 /* IRQ stack memory (calculated at run-time) */
85 .globl IRQ_STACK_START
89 /* IRQ stack memory (calculated at run-time) */
90 .globl FIQ_STACK_START
93 #endif /* CONFIG_USE_IRQ */
96 /****************************************************************************/
98 /* the actual reset code */
100 /****************************************************************************/
103 mrs r0,cpsr /* set the CPU to SVC32 mode */
104 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
109 * we do sys-critical inits only at reboot,
110 * not when booting from RAM!
112 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
113 bl cpu_init_crit /* we do sys-critical inits */
114 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
116 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
117 relocate: /* relocate U-Boot to RAM */
118 adr r0, _start /* r0 <- current position of code */
119 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
120 cmp r0, r1 /* don't reloc during debug */
123 ldr r2, _armboot_start
125 sub r2, r3, r2 /* r2 <- size of armboot */
126 add r2, r0, r2 /* r2 <- source end address */
129 ldmia r0!, {r3-r10} /* copy from source address [r0] */
130 stmia r1!, {r3-r10} /* copy to target address [r1] */
131 cmp r0, r2 /* until source end address [r2] */
133 #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
135 /* Set up the stack */
137 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
138 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
139 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
140 #ifdef CONFIG_USE_IRQ
141 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
142 #endif /* CONFIG_USE_IRQ */
143 sub r0, r0, #12 /* leave 3 words for abort-stack */
144 bic sp, r0, #7 /* NOTE: stack MUST be aligned to */
145 /* 8 bytes in case we want to use */
146 /* 64bit datatypes (eg. VSPRINTF64) */
149 ldr r0, _bss_start /* find start of bss segment */
150 ldr r1, _bss_end /* stop here */
151 mov r2, #0x00000000 /* clear */
153 clbss_l:str r2, [r0] /* clear loop... */
158 ldr pc, _start_armboot
160 _start_armboot: .word start_armboot
163 /****************************************************************************/
165 /* CPU_init_critical registers */
167 /* - setup important registers */
168 /* - setup memory timing */
170 /****************************************************************************/
171 /* mk@tbd: Fix this! */
180 /* Interrupt-Controller base address */
181 IC_BASE: .word 0x40d00000
184 /* Reset-Controller */
185 RST_BASE: .word 0x40f00030
188 /* Operating System Timer */
189 OSTIMER_BASE: .word 0x40a00000
195 /* Clock Manager Registers */
196 #ifdef CONFIG_CPU_MONAHANS
197 # ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
198 # error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
199 # endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
200 # ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
201 # define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
202 # endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
203 #else /* !CONFIG_CPU_MONAHANS */
204 #ifdef CONFIG_SYS_CPUSPEED
205 CC_BASE: .word 0x41300000
207 cpuspeed: .word CONFIG_SYS_CPUSPEED
208 #else /* !CONFIG_SYS_CPUSPEED */
209 #error "You have to define CONFIG_SYS_CPUSPEED!!"
210 #endif /* CONFIG_SYS_CPUSPEED */
211 #endif /* CONFIG_CPU_MONAHANS */
213 /* takes care the CP15 update has taken place */
215 mrc p15,0,\reg,c2,c0,0
223 #ifndef CONFIG_CPU_MONAHANS
227 #else /* CONFIG_CPU_MONAHANS */
228 /* Step 1 - Enable CP6 permission */
229 mrc p15, 0, r1, c15, c1, 0 @ read CPAR
231 mcr p15, 0, r1, c15, c1, 0
234 /* Step 2 - Mask ICMR & ICMR2 */
236 mcr p6, 0, r1, c1, c0, 0 @ ICMR
237 mcr p6, 0, r1, c7, c0, 0 @ ICMR2
239 /* turn off all clocks but the ones we will definitly require */
241 ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
244 ldr r2, =(CKENB_6_IRQ)
246 #endif /* !CONFIG_CPU_MONAHANS */
248 /* set clock speed */
249 #ifdef CONFIG_CPU_MONAHANS
251 ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
253 #else /* !CONFIG_CPU_MONAHANS */
254 #ifdef CONFIG_SYS_CPUSPEED
259 mcr p14, 0, r0, c6, c0, 0
263 #endif /* CONFIG_SYS_CPUSPEED */
264 #endif /* CONFIG_CPU_MONAHANS */
267 * before relocating, we have to setup RAM timing
268 * because memory timing is board-dependend, you will
269 * find a lowlevel_init.S in your board directory.
275 /* Memory interfaces are working. Disable MMU and enable I-cache. */
276 /* mk: hmm, this is not in the monahans docs, leave it now but
277 * check here if it doesn't work :-) */
279 ldr r0, =0x2001 /* enable access to all coproc. */
280 mcr p15, 0, r0, c15, c1, 0
283 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
286 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
289 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
292 /* Enable the Icache */
294 mrc p15, 0, r0, c1, c0, 0
296 mcr p15, 0, r0, c1, c0, 0
302 /****************************************************************************/
304 /* Interrupt handling */
306 /****************************************************************************/
308 /* IRQ stack frame */
310 #define S_FRAME_SIZE 72
332 #define MODE_SVC 0x13
334 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
336 .macro bad_save_user_regs
337 sub sp, sp, #S_FRAME_SIZE
338 stmia sp, {r0 - r12} /* Calling r0-r12 */
341 ldr r2, _armboot_start
342 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
343 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
344 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
345 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
349 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
354 /* use irq_save_user_regs / irq_restore_user_regs for */
355 /* IRQ/FIQ handling */
357 .macro irq_save_user_regs
358 sub sp, sp, #S_FRAME_SIZE
359 stmia sp, {r0 - r12} /* Calling r0-r12 */
361 stmdb r8, {sp, lr}^ /* Calling SP, LR */
362 str lr, [r8, #0] /* Save calling PC */
364 str r6, [r8, #4] /* Save CPSR */
365 str r0, [r8, #8] /* Save OLD_R0 */
369 .macro irq_restore_user_regs
370 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
372 ldr lr, [sp, #S_PC] @ Get PC
373 add sp, sp, #S_FRAME_SIZE
374 subs pc, lr, #4 @ return & move spsr_svc into cpsr
378 ldr r13, _armboot_start @ setup our mode stack
379 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
380 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
382 str lr, [r13] @ save caller lr / spsr
386 mov r13, #MODE_SVC @ prepare SVC-Mode
392 .macro get_irq_stack @ setup IRQ stack
393 ldr sp, IRQ_STACK_START
396 .macro get_fiq_stack @ setup FIQ stack
397 ldr sp, FIQ_STACK_START
401 /****************************************************************************/
403 /* exception handlers */
405 /****************************************************************************/
408 undefined_instruction:
411 bl do_undefined_instruction
417 bl do_software_interrupt
437 #ifdef CONFIG_USE_IRQ
444 irq_restore_user_regs
449 irq_save_user_regs /* someone ought to write a more */
450 bl do_fiq /* effiction fiq_save_user_regs */
451 irq_restore_user_regs
453 #else /* !CONFIG_USE_IRQ */
467 #endif /* CONFIG_USE_IRQ */
469 /****************************************************************************/
471 /* Reset function: the PXA250 doesn't have a reset function, so we have to */
472 /* perform a watchdog timeout for a soft reset. */
474 /****************************************************************************/
479 /* FIXME: this code is PXA250 specific. How is this handled on */
480 /* other XScale processors? */
484 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
488 orr r1, r1, #0x0001 /* bit0: WME */
491 /* OS timer does only wrap every 1165 seconds, so we have to set */
492 /* the match register as well. */
494 ldr r1, [r0, #OSCR] /* read OS timer */
495 add r1, r1, #0x800 /* let OSMR3 match after */
496 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */