2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/pxa-regs.h>
34 #include <asm/arch/macro.h>
36 /* takes care the CP15 update has taken place */
38 mrc p15,0,\reg,c2,c0,0
45 #ifdef CONFIG_PRELOADER
62 .word 0x12345678 /* now 16*4=64 */
64 ldr pc, _undefined_instruction
65 ldr pc, _software_interrupt
66 ldr pc, _prefetch_abort
72 _undefined_instruction: .word undefined_instruction
73 _software_interrupt: .word software_interrupt
74 _prefetch_abort: .word prefetch_abort
75 _data_abort: .word data_abort
76 _not_used: .word not_used
79 #endif /* CONFIG_PRELOADER */
81 .balignl 16,0xdeadbeef
85 * Startup Code (reset vector)
87 * do important init only if we don't start from RAM!
88 * - relocate armboot to RAM
90 * - jump to second stage
95 .word CONFIG_SYS_TEXT_BASE
102 * These are defined in the board-specific linker script.
112 #ifdef CONFIG_USE_IRQ
113 /* IRQ stack memory (calculated at run-time) */
114 .globl IRQ_STACK_START
118 /* IRQ stack memory (calculated at run-time) */
119 .globl FIQ_STACK_START
122 #endif /* CONFIG_USE_IRQ */
124 #ifndef CONFIG_PRELOADER
125 /* IRQ stack memory (calculated at run-time) + 8 bytes */
126 .globl IRQ_STACK_START_IN
130 .globl _datarel_start
132 .word __datarel_start
134 .globl _datarelrolocal_start
135 _datarelrolocal_start:
136 .word __datarelrolocal_start
138 .globl _datarellocal_start
140 .word __datarellocal_start
142 .globl _datarelro_start
144 .word __datarelro_start
155 * the actual reset code
160 * set the cpu to SVC32 mode
168 * Enable MMU to use DCache as DRAM
170 /* Domain access -- enable for all CPs */
172 mcr p15, 0, r0, c3, c0, 0
174 /* Point TTBR to MMU table */
178 mcr p15, 0, r0, c2, c0, 0
180 /* !!! Hereby, check if the code is running from SRAM !!! */
181 /* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
182 * is linked to 0x0 too, so this makes things easier. */
189 /* Kick in MMU, ICache, DCache, BTB */
190 mrc p15, 0, r0, c1, c0, 0
195 mcr p15, 0, r0, c1, c0, 0
198 /* Unlock Icache, Dcache */
199 mcr p15, 0, r0, c9, c1, 1
200 mcr p15, 0, r0, c9, c2, 1
202 /* Flush Icache, Dcache, BTB */
203 mcr p15, 0, r0, c7, c7, 0
205 /* Unlock I-TLB, D-TLB */
206 mcr p15, 0, r0, c10, c4, 1
207 mcr p15, 0, r0, c10, c8, 1
210 mcr p15, 0, r0, c8, c7, 0
211 /* Allocate 4096 bytes of Dcache as RAM */
213 /* Drain pending loads and stores */
214 mcr p15, 0, r0, c7, c10, 4
219 mcr p15, 0, r0, c9, c2, 0
222 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
226 mcr p15, 0, r1, c7, c2, 5
227 /* Drain pending loads and stores */
228 mcr p15, 0, r0, c7, c10, 4
235 /* Drain pending loads and stores */
236 mcr p15, 0, r0, c7, c10, 4
238 mcr p15, 0, r2, c9, c2, 0
241 /* Jump to 0x0 ( + offset) if running from SRAM */
247 /* Set stackpointer in internal RAM to call board_init_f */
249 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
253 /*------------------------------------------------------------------------------*/
256 * void relocate_code (addr_sp, gd, addr_moni)
258 * This "function" does not return, instead it continues in RAM
259 * after relocating the monitor code.
264 mov r4, r0 /* save addr_sp */
265 mov r5, r1 /* save addr of gd */
266 mov r6, r2 /* save addr of destination */
267 mov r7, r2 /* save addr of destination */
269 /* Set up the stack */
276 sub r2, r3, r2 /* r2 <- size of armboot */
277 add r2, r0, r2 /* r2 <- source end address */
281 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
284 ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
285 stmia r6!, {r3-r5, r7-r11} /* copy to target address [r1] */
286 cmp r0, r2 /* until source end address [r2] */
290 #ifndef CONFIG_PRELOADER
291 /* fix got entries */
292 ldr r1, _TEXT_BASE /* Text base */
293 mov r0, r7 /* reloc addr */
294 ldr r2, _got_start /* addr in Flash */
295 ldr r3, _got_end /* addr in Flash */
310 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
313 #ifndef CONFIG_PRELOADER
316 ldr r3, _TEXT_BASE /* Text base */
317 mov r4, r7 /* reloc addr */
322 mov r2, #0x00000000 /* clear */
324 clbss_l:str r2, [r0] /* clear loop... */
331 * We are done. Do not return, instead branch to second part of board
332 * initialization, now running from RAM.
334 #ifdef CONFIG_ONENAND_IPL
335 ldr pc, _start_oneboot
337 _start_oneboot: .word start_oneboot
340 ldr r2, _board_init_r
342 add r2, r2, r7 /* position from board_init_r in RAM */
343 /* setup parameters for board_init_r */
344 mov r0, r5 /* gd_t */
345 mov r1, r7 /* dest_addr */
350 _board_init_r: .word board_init_r
353 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
355 /****************************************************************************/
357 /* the actual reset code for OneNAND IPL */
359 /****************************************************************************/
361 #ifndef CONFIG_PXA27X
362 #error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
366 /* Set CPU to SVC32 mode */
372 /* Point stack at the end of SRAM and leave 32 words for abort-stack */
375 /* Start OneNAND IPL */
376 ldr pc, =start_oneboot
378 #endif /* #if !defined(CONFIG_ONENAND_IPL) */
380 #ifndef CONFIG_PRELOADER
381 /****************************************************************************/
383 /* Interrupt handling */
385 /****************************************************************************/
387 /* IRQ stack frame */
389 #define S_FRAME_SIZE 72
411 #define MODE_SVC 0x13
413 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
415 .macro bad_save_user_regs
416 sub sp, sp, #S_FRAME_SIZE
417 stmia sp, {r0 - r12} /* Calling r0-r12 */
420 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
421 ldr r2, _armboot_start
422 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
423 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
425 ldr r2, IRQ_STACK_START_IN
427 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
428 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
432 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
437 /* use irq_save_user_regs / irq_restore_user_regs for */
438 /* IRQ/FIQ handling */
440 .macro irq_save_user_regs
441 sub sp, sp, #S_FRAME_SIZE
442 stmia sp, {r0 - r12} /* Calling r0-r12 */
444 stmdb r8, {sp, lr}^ /* Calling SP, LR */
445 str lr, [r8, #0] /* Save calling PC */
447 str r6, [r8, #4] /* Save CPSR */
448 str r0, [r8, #8] /* Save OLD_R0 */
452 .macro irq_restore_user_regs
453 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
455 ldr lr, [sp, #S_PC] @ Get PC
456 add sp, sp, #S_FRAME_SIZE
457 subs pc, lr, #4 @ return & move spsr_svc into cpsr
461 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
462 ldr r13, _armboot_start @ setup our mode stack
463 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
464 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
466 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
469 str lr, [r13] @ save caller lr / spsr
473 mov r13, #MODE_SVC @ prepare SVC-Mode
479 .macro get_irq_stack @ setup IRQ stack
480 ldr sp, IRQ_STACK_START
483 .macro get_fiq_stack @ setup FIQ stack
484 ldr sp, FIQ_STACK_START
486 #endif /* CONFIG_PRELOADER */
489 /****************************************************************************/
491 /* exception handlers */
493 /****************************************************************************/
495 #ifdef CONFIG_PRELOADER
498 ldr sp, _TEXT_BASE /* use 32 words abort stack */
499 bl hang /* hang and never return */
500 #else /* !CONFIG_PRELOADER */
502 undefined_instruction:
505 bl do_undefined_instruction
511 bl do_software_interrupt
531 #ifdef CONFIG_USE_IRQ
538 irq_restore_user_regs
543 irq_save_user_regs /* someone ought to write a more */
544 bl do_fiq /* effiction fiq_save_user_regs */
545 irq_restore_user_regs
547 #else /* !CONFIG_USE_IRQ */
560 #endif /* CONFIG_PRELOADER */
561 #endif /* CONFIG_USE_IRQ */
563 /****************************************************************************/
565 /* Reset function: the PXA250 doesn't have a reset function, so we have to */
566 /* perform a watchdog timeout for a soft reset. */
568 /****************************************************************************/
569 /* Operating System Timer */
570 OSTIMER_BASE: .word 0x40a00000
579 /* FIXME: this code is PXA250 specific. How is this handled on */
580 /* other XScale processors? */
584 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
588 orr r1, r1, #0x0001 /* bit0: WME */
591 /* OS timer does only wrap every 1165 seconds, so we have to set */
592 /* the match register as well. */
594 ldr r1, [r0, #OSCR] /* read OS timer */
595 add r1, r1, #0x800 /* let OSMR3 match after */
596 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
603 #ifndef CONFIG_PRELOADER
604 .section .mmudata, "a"
608 /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
611 .word (__base << 20) | 0xc12
612 .set __base, __base + 1
615 /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
616 .word (0xa00 << 20) | 0x1c1e
620 .word (__base << 20) | 0xc12
621 .set __base, __base + 1