arch/arm/cpu/pxa/pxafb.c

   1 /*
   2  * PXA LCD Controller
   3  *
   4  * (C) Copyright 2001-2002
   5  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************/
  27 /* ** HEADER FILES                                                      */
  28 /************************************************************************/
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <version.h>
  33 #include <stdarg.h>
  34 #include <linux/types.h>
  35 #include <stdio_dev.h>
  36 #include <lcd.h>
  37 #include <asm/arch/pxa-regs.h>
  38 #include <asm/io.h>
  39
  40 /* #define DEBUG */
  41
  42 #ifdef CONFIG_LCD
  43
  44 /*----------------------------------------------------------------------*/
  45 /*
  46  * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  47  * your display.
  48  */
  49
  50 #ifdef CONFIG_PXA_VGA
  51 /* LCD outputs connected to a video DAC  */
  52 # define LCD_BPP        LCD_COLOR8
  53
  54 /* you have to set lccr0 and lccr3 (including pcd) */
  55 # define REG_LCCR0      0x003008f8
  56 # define REG_LCCR3      0x0300FF01
  57
  58 /* 640x480x16 @ 61 Hz */
  59 vidinfo_t panel_info = {
  60         .vl_col         = 640,
  61         .vl_row         = 480,
  62         .vl_width       = 640,
  63         .vl_height      = 480,
  64         .vl_clkp        = CONFIG_SYS_HIGH,
  65         .vl_oep         = CONFIG_SYS_HIGH,
  66         .vl_hsp         = CONFIG_SYS_HIGH,
  67         .vl_vsp         = CONFIG_SYS_HIGH,
  68         .vl_dp          = CONFIG_SYS_HIGH,
  69         .vl_bpix        = LCD_BPP,
  70         .vl_lbw         = 0,
  71         .vl_splt        = 0,
  72         .vl_clor        = 0,
  73         .vl_tft         = 1,
  74         .vl_hpw         = 40,
  75         .vl_blw         = 56,
  76         .vl_elw         = 56,
  77         .vl_vpw         = 20,
  78         .vl_bfw         = 8,
  79         .vl_efw         = 8,
  80 };
  81 #endif /* CONFIG_PXA_VIDEO */
  82
  83 /*----------------------------------------------------------------------*/
  84 #ifdef CONFIG_SHARP_LM8V31
  85
  86 # define LCD_BPP        LCD_COLOR8
  87 # define LCD_INVERT_COLORS      /* Needed for colors to be correct, but why?    */
  88
  89 /* you have to set lccr0 and lccr3 (including pcd) */
  90 # define REG_LCCR0      0x0030087C
  91 # define REG_LCCR3      0x0340FF08
  92
  93 vidinfo_t panel_info = {
  94         .vl_col         = 640,
  95         .vl_row         = 480,
  96         .vl_width       = 157,
  97         .vl_height      = 118,
  98         .vl_clkp        = CONFIG_SYS_HIGH,
  99         .vl_oep         = CONFIG_SYS_HIGH,
 100         .vl_hsp         = CONFIG_SYS_HIGH,
 101         .vl_vsp         = CONFIG_SYS_HIGH,
 102         .vl_dp          = CONFIG_SYS_HIGH,
 103         .vl_bpix        = LCD_BPP,
 104         .vl_lbw         = 0,
 105         .vl_splt        = 1,
 106         .vl_clor        = 1,
 107         .vl_tft         = 0,
 108         .vl_hpw         = 1,
 109         .vl_blw         = 3,
 110         .vl_elw         = 3,
 111         .vl_vpw         = 1,
 112         .vl_bfw         = 0,
 113         .vl_efw         = 0,
 114 };
 115 #endif /* CONFIG_SHARP_LM8V31 */
 116 /*----------------------------------------------------------------------*/
 117 #ifdef CONFIG_VOIPAC_LCD
 118
 119 # define LCD_BPP        LCD_COLOR8
 120 # define LCD_INVERT_COLORS
 121
 122 /* you have to set lccr0 and lccr3 (including pcd) */
 123 # define REG_LCCR0      0x043008f8
 124 # define REG_LCCR3      0x0340FF08
 125
 126 vidinfo_t panel_info = {
 127         .vl_col         = 640,
 128         .vl_row         = 480,
 129         .vl_width       = 157,
 130         .vl_height      = 118,
 131         .vl_clkp        = CONFIG_SYS_HIGH,
 132         .vl_oep         = CONFIG_SYS_HIGH,
 133         .vl_hsp         = CONFIG_SYS_HIGH,
 134         .vl_vsp         = CONFIG_SYS_HIGH,
 135         .vl_dp          = CONFIG_SYS_HIGH,
 136         .vl_bpix        = LCD_BPP,
 137         .vl_lbw         = 0,
 138         .vl_splt        = 1,
 139         .vl_clor        = 1,
 140         .vl_tft         = 1,
 141         .vl_hpw         = 32,
 142         .vl_blw         = 144,
 143         .vl_elw         = 32,
 144         .vl_vpw         = 2,
 145         .vl_bfw         = 13,
 146         .vl_efw         = 30,
 147 };
 148 #endif /* CONFIG_VOIPAC_LCD */
 149
 150 /*----------------------------------------------------------------------*/
 151 #ifdef CONFIG_HITACHI_SX14
 152 /* Hitachi SX14Q004-ZZA color STN LCD */
 153 #define LCD_BPP         LCD_COLOR8
 154
 155 /* you have to set lccr0 and lccr3 (including pcd) */
 156 #define REG_LCCR0       0x00301079
 157 #define REG_LCCR3       0x0340FF20
 158
 159 vidinfo_t panel_info = {
 160         .vl_col         = 320,
 161         .vl_row         = 240,
 162         .vl_width       = 167,
 163         .vl_height      = 109,
 164         .vl_clkp        = CONFIG_SYS_HIGH,
 165         .vl_oep         = CONFIG_SYS_HIGH,
 166         .vl_hsp         = CONFIG_SYS_HIGH,
 167         .vl_vsp         = CONFIG_SYS_HIGH,
 168         .vl_dp          = CONFIG_SYS_HIGH,
 169         .vl_bpix        = LCD_BPP,
 170         .vl_lbw         = 1,
 171         .vl_splt        = 0,
 172         .vl_clor        = 1,
 173         .vl_tft         = 0,
 174         .vl_hpw         = 1,
 175         .vl_blw         = 1,
 176         .vl_elw         = 1,
 177         .vl_vpw         = 7,
 178         .vl_bfw         = 0,
 179         .vl_efw         = 0,
 180 };
 181 #endif /* CONFIG_HITACHI_SX14 */
 182
 183 /*----------------------------------------------------------------------*/
 184 #ifdef CONFIG_LMS283GF05
 185
 186 # define LCD_BPP        LCD_COLOR8
 187 /*# define LCD_INVERT_COLORS*/
 188
 189 /* you have to set lccr0 and lccr3 (including pcd) */
 190 # define REG_LCCR0      0x043008f8
 191 # define REG_LCCR3      0x03b00009
 192
 193 vidinfo_t panel_info = {
 194         .vl_col         = 240,
 195         .vl_row         = 320,
 196         .vl_width       = 240,
 197         .vl_height      = 320,
 198         .vl_clkp        = CONFIG_SYS_HIGH,
 199         .vl_oep         = CONFIG_SYS_LOW,
 200         .vl_hsp         = CONFIG_SYS_LOW,
 201         .vl_vsp         = CONFIG_SYS_LOW,
 202         .vl_dp          = CONFIG_SYS_HIGH,
 203         .vl_bpix        = LCD_BPP,
 204         .vl_lbw         = 0,
 205         .vl_splt        = 1,
 206         .vl_clor        = 1,
 207         .vl_tft         = 1,
 208         .vl_hpw         = 4,
 209         .vl_blw         = 4,
 210         .vl_elw         = 8,
 211         .vl_vpw         = 4,
 212         .vl_bfw         = 4,
 213         .vl_efw         = 8,
 214 };
 215 #endif /* CONFIG_LMS283GF05 */
 216
 217 /*----------------------------------------------------------------------*/
 218
 219 #ifdef CONFIG_ACX517AKN
 220
 221 # define LCD_BPP        LCD_COLOR8
 222
 223 /* you have to set lccr0 and lccr3 (including pcd) */
 224 # define REG_LCCR0      0x003008f9
 225 # define REG_LCCR3      0x03700006
 226
 227 vidinfo_t panel_info = {
 228         .vl_col         = 320,
 229         .vl_row         = 320,
 230         .vl_width       = 320,
 231         .vl_height      = 320,
 232         .vl_clkp        = CONFIG_SYS_HIGH,
 233         .vl_oep         = CONFIG_SYS_LOW,
 234         .vl_hsp         = CONFIG_SYS_LOW,
 235         .vl_vsp         = CONFIG_SYS_LOW,
 236         .vl_dp          = CONFIG_SYS_HIGH,
 237         .vl_bpix        = LCD_BPP,
 238         .vl_lbw         = 0,
 239         .vl_splt        = 1,
 240         .vl_clor        = 1,
 241         .vl_tft         = 1,
 242         .vl_hpw         = 0x04,
 243         .vl_blw         = 0x1c,
 244         .vl_elw         = 0x08,
 245         .vl_vpw         = 0x01,
 246         .vl_bfw         = 0x07,
 247         .vl_efw         = 0x08,
 248 };
 249 #endif /* CONFIG_ACX517AKN */
 250
 251 /*----------------------------------------------------------------------*/
 252
 253 #if LCD_BPP == LCD_COLOR8
 254 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 255 #endif
 256 #if LCD_BPP == LCD_MONOCHROME
 257 void lcd_initcolregs (void);
 258 #endif
 259
 260 #ifdef NOT_USED_SO_FAR
 261 void lcd_disable (void);
 262 void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
 263 #endif /* NOT_USED_SO_FAR */
 264
 265 void lcd_ctrl_init      (void *lcdbase);
 266 void lcd_enable (void);
 267
 268 int lcd_line_length;
 269 int lcd_color_fg;
 270 int lcd_color_bg;
 271
 272 void *lcd_base;                 /* Start of framebuffer memory  */
 273 void *lcd_console_address;              /* Start of console buffer      */
 274
 275 short console_col;
 276 short console_row;
 277
 278 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
 279 static void pxafb_setup_gpio (vidinfo_t *vid);
 280 static void pxafb_enable_controller (vidinfo_t *vid);
 281 static int pxafb_init (vidinfo_t *vid);
 282 /************************************************************************/
 283
 284 /************************************************************************/
 285 /* ---------------  PXA chipset specific functions  ------------------- */
 286 /************************************************************************/
 287
 288 void lcd_ctrl_init (void *lcdbase)
 289 {
 290         pxafb_init_mem(lcdbase, &panel_info);
 291         pxafb_init(&panel_info);
 292         pxafb_setup_gpio(&panel_info);
 293         pxafb_enable_controller(&panel_info);
 294 }
 295
 296 /*----------------------------------------------------------------------*/
 297 #ifdef NOT_USED_SO_FAR
 298 void
 299 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
 300 {
 301 }
 302 #endif /* NOT_USED_SO_FAR */
 303
 304 /*----------------------------------------------------------------------*/
 305 #if LCD_BPP == LCD_COLOR8
 306 void
 307 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 308 {
 309         struct pxafb_info *fbi = &panel_info.pxa;
 310         unsigned short *palette = (unsigned short *)fbi->palette;
 311         u_int val;
 312
 313         if (regno < fbi->palette_size) {
 314                 val = ((red << 8) & 0xf800);
 315                 val |= ((green << 4) & 0x07e0);
 316                 val |= (blue & 0x001f);
 317
 318 #ifdef LCD_INVERT_COLORS
 319                 palette[regno] = ~val;
 320 #else
 321                 palette[regno] = val;
 322 #endif
 323         }
 324
 325         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
 326                 regno, &palette[regno],
 327                 red, green, blue,
 328                 palette[regno]);
 329 }
 330 #endif /* LCD_COLOR8 */
 331
 332 /*----------------------------------------------------------------------*/
 333 #if LCD_BPP == LCD_MONOCHROME
 334 void lcd_initcolregs (void)
 335 {
 336         struct pxafb_info *fbi = &panel_info.pxa;
 337         cmap = (ushort *)fbi->palette;
 338         ushort regno;
 339
 340         for (regno = 0; regno < 16; regno++) {
 341                 cmap[regno * 2] = 0;
 342                 cmap[(regno * 2) + 1] = regno & 0x0f;
 343         }
 344 }
 345 #endif /* LCD_MONOCHROME */
 346
 347 /*----------------------------------------------------------------------*/
 348 void lcd_enable (void)
 349 {
 350 }
 351
 352 /*----------------------------------------------------------------------*/
 353 #ifdef  NOT_USED_SO_FAR
 354 static void lcd_disable (void)
 355 {
 356 }
 357 #endif /* NOT_USED_SO_FAR */
 358
 359 /*----------------------------------------------------------------------*/
 360
 361 /************************************************************************/
 362 /* ** PXA255 specific routines                                          */
 363 /************************************************************************/
 364
 365 /*
 366  * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 367  * descriptors and palette areas.
 368  */
 369 ulong calc_fbsize (void)
 370 {
 371         ulong size;
 372         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 373
 374         size = line_length * panel_info.vl_row;
 375         size += PAGE_SIZE;
 376
 377         return size;
 378 }
 379
 380 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 381 {
 382         u_long palette_mem_size;
 383         struct pxafb_info *fbi = &vid->pxa;
 384         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 385
 386         fbi->screen = (u_long)lcdbase;
 387
 388         fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
 389         palette_mem_size = fbi->palette_size * sizeof(u16);
 390
 391         debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 392         /* locate palette and descs at end of page following fb */
 393         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 394
 395         return 0;
 396 }
 397 #ifdef  CONFIG_CPU_MONAHANS
 398 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
 399 #else
 400 static void pxafb_setup_gpio (vidinfo_t *vid)
 401 {
 402         u_long lccr0;
 403
 404         /*
 405          * setup is based on type of panel supported
 406          */
 407
 408         lccr0 = vid->pxa.reg_lccr0;
 409
 410         /* 4 bit interface */
 411         if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
 412         {
 413                 debug("Setting GPIO for 4 bit data\n");
 414                 /* bits 58-61 */
 415                 writel(readl(GPDR1) | (0xf << 26), GPDR1);
 416                 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
 417                         GAFR1_U);
 418
 419                 /* bits 74-77 */
 420                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 421                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 422                         GAFR2_L);
 423         }
 424
 425         /* 8 bit interface */
 426         else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
 427                 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
 428         {
 429                 debug("Setting GPIO for 8 bit data\n");
 430                 /* bits 58-65 */
 431                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 432                 writel(readl(GPDR2) | (0x3), GPDR2);
 433
 434                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 435                         GAFR1_U);
 436                 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
 437
 438                 /* bits 74-77 */
 439                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 440                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 441                         GAFR2_L);
 442         }
 443
 444         /* 16 bit interface */
 445         else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
 446         {
 447                 debug("Setting GPIO for 16 bit data\n");
 448                 /* bits 58-77 */
 449                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 450                 writel(readl(GPDR2) | 0x00003fff, GPDR2);
 451
 452                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 453                         GAFR1_U);
 454                 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
 455         }
 456         else
 457         {
 458                 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 459         }
 460 }
 461 #endif
 462
 463 static void pxafb_enable_controller (vidinfo_t *vid)
 464 {
 465         debug("Enabling LCD controller\n");
 466
 467         /* Sequence from 11.7.10 */
 468         writel(vid->pxa.reg_lccr3, LCCR3);
 469         writel(vid->pxa.reg_lccr2, LCCR2);
 470         writel(vid->pxa.reg_lccr1, LCCR1);
 471         writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
 472         writel(vid->pxa.fdadr0, FDADR0);
 473         writel(vid->pxa.fdadr1, FDADR1);
 474         writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
 475
 476 #ifdef  CONFIG_CPU_MONAHANS
 477         writel(readl(CKENA) | CKENA_1_LCD, CKENA);
 478 #else
 479         writel(readl(CKEN) | CKEN16_LCD, CKEN);
 480 #endif
 481
 482         debug("FDADR0 = 0x%08x\n", readl(FDADR0));
 483         debug("FDADR1 = 0x%08x\n", readl(FDADR1));
 484         debug("LCCR0 = 0x%08x\n", readl(LCCR0));
 485         debug("LCCR1 = 0x%08x\n", readl(LCCR1));
 486         debug("LCCR2 = 0x%08x\n", readl(LCCR2));
 487         debug("LCCR3 = 0x%08x\n", readl(LCCR3));
 488 }
 489
 490 static int pxafb_init (vidinfo_t *vid)
 491 {
 492         struct pxafb_info *fbi = &vid->pxa;
 493
 494         debug("Configuring PXA LCD\n");
 495
 496         fbi->reg_lccr0 = REG_LCCR0;
 497         fbi->reg_lccr3 = REG_LCCR3;
 498
 499         debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
 500                 vid->vl_col, vid->vl_hpw,
 501                 vid->vl_blw, vid->vl_elw);
 502         debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
 503                 vid->vl_row, vid->vl_vpw,
 504                 vid->vl_bfw, vid->vl_efw);
 505
 506         fbi->reg_lccr1 =
 507                 LCCR1_DisWdth(vid->vl_col) +
 508                 LCCR1_HorSnchWdth(vid->vl_hpw) +
 509                 LCCR1_BegLnDel(vid->vl_blw) +
 510                 LCCR1_EndLnDel(vid->vl_elw);
 511
 512         fbi->reg_lccr2 =
 513                 LCCR2_DisHght(vid->vl_row) +
 514                 LCCR2_VrtSnchWdth(vid->vl_vpw) +
 515                 LCCR2_BegFrmDel(vid->vl_bfw) +
 516                 LCCR2_EndFrmDel(vid->vl_efw);
 517
 518         fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
 519         fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
 520                         | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
 521
 522
 523         /* setup dma descriptors */
 524         fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 525         fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 526         fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 527
 528         #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
 529                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
 530                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
 531
 532         /* populate descriptors */
 533         fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
 534         fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
 535         fbi->dmadesc_fblow->fidr  = 0;
 536         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 537
 538         fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
 539
 540         fbi->dmadesc_fbhigh->fsadr = fbi->screen;
 541         fbi->dmadesc_fbhigh->fidr = 0;
 542         fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
 543
 544         fbi->dmadesc_palette->fsadr = fbi->palette;
 545         fbi->dmadesc_palette->fidr  = 0;
 546         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 547
 548         if( NBITS(vid->vl_bpix) < 12)
 549         {
 550                 /* assume any mode with <12 bpp is palette driven */
 551                 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
 552                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
 553                 /* flips back and forth between pal and fbhigh */
 554                 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
 555         }
 556         else
 557         {
 558                 /* palette shouldn't be loaded in true-color mode */
 559                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
 560                 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
 561         }
 562
 563         debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
 564         debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
 565         debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
 566
 567         debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
 568         debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
 569         debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
 570
 571         debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
 572         debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
 573         debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
 574
 575         debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
 576         debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
 577         debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
 578
 579         return 0;
 580 }
 581
 582 /************************************************************************/
 583 /************************************************************************/
 584
 585 #endif /* CONFIG_LCD */