1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
13 #include <asm/arch/pxa-regs.h>
15 #include <asm/system.h>
19 static void cache_flush(void)
23 asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
26 int cleanup_before_linux(void)
29 * This function is called just before we call Linux. It prepares
30 * the processor for Linux by just disabling everything that can
31 * disturb booting Linux.
42 inline void writelrb(uint32_t val, uint32_t addr)
45 asm volatile("" : : : "memory");
47 asm volatile("" : : : "memory");
50 void pxa2xx_dram_init(void)
55 * 1) Initialize Asynchronous static memory controller
58 writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
59 writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
60 writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
62 * 2) Initialize Card Interface
65 /* MECR: Memory Expansion Card Register */
66 writelrb(CONFIG_SYS_MECR_VAL, MECR);
67 /* MCMEM0: Card Interface slot 0 timing */
68 writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
69 /* MCMEM1: Card Interface slot 1 timing */
70 writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
71 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
72 writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
73 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
74 writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
75 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
76 writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
77 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
78 writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
81 * 3) Configure Fly-By DMA register
84 writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
87 * 4) Initialize Timing for Sync Memory (SDCLK0)
91 * Before accessing MDREFR we need a valid DRI field, so we set
92 * this to power on defaults + DRI field.
95 /* Read current MDREFR config and zero out DRI */
96 tmp = readl(MDREFR) & ~0xfff;
97 /* Add user-specified DRI */
98 tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
99 /* Configure important bits */
100 tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
101 tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
103 /* Write MDREFR back */
104 writelrb(tmp, MDREFR);
107 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
110 /* Initialize SXCNFG register. Assert the enable bits.
112 * Write SXMRS to cause an MRS command to all enabled banks of
113 * synchronous static memory. Note that SXLCR need not be written
116 writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
119 * 6) Initialize SDRAM
122 writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
123 writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
126 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
127 * but not enable each SDRAM partition pair.
130 writelrb(CONFIG_SYS_MDCNFG_VAL &
131 ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
133 /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
135 while (readl(OSCR) < 0x300)
136 asm volatile("" : : : "memory");
139 * 8) Trigger a number (usually 8) refresh cycles by attempting
140 * non-burst read or write accesses to disabled SDRAM, as commonly
141 * specified in the power up sequence documented in SDRAM data
142 * sheets. The address(es) used for this purpose must not be
145 for (i = 9; i >= 0; i--) {
146 writel(i, 0xa0000000);
147 asm volatile("" : : : "memory");
150 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
153 tmp = CONFIG_SYS_MDCNFG_VAL &
154 (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
155 tmp |= readl(MDCNFG);
156 writelrb(tmp, MDCNFG);
162 writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
168 if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
171 writelrb(tmp, MDREFR);
175 void pxa_gpio_setup(void)
177 writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
178 writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
179 writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
180 #if defined(CONFIG_CPU_PXA27X)
181 writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
184 writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
185 writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
186 writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
187 #if defined(CONFIG_CPU_PXA27X)
188 writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
191 writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
192 writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
193 writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
194 #if defined(CONFIG_CPU_PXA27X)
195 writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
198 writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
199 writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
200 writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
201 writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
202 writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
203 writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
204 #if defined(CONFIG_CPU_PXA27X)
205 writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
206 writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
209 writel(CONFIG_SYS_PSSR_VAL, PSSR);
212 void pxa_interrupt_setup(void)
216 #if defined(CONFIG_CPU_PXA27X)
222 void pxa_clock_setup(void)
224 writel(CONFIG_SYS_CKEN, CKEN);
225 writel(CONFIG_SYS_CCCR, CCCR);
226 asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
228 /* enable the 32Khz oscillator for RTC and PowerManager */
229 writel(OSCC_OON, OSCC);
230 while (!(readl(OSCC) & OSCC_OOK))
231 asm volatile("" : : : "memory");
234 void pxa_wakeup(void)
239 writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
242 if (rcsr & RCSR_SMR) {
243 writel(PSSR_PH, PSSR);
247 asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
251 int arch_cpu_init(void)
255 pxa_interrupt_setup();
260 void i2c_clk_enable(void)
262 /* Set the global I2C clock on */
263 writel(readl(CKEN) | CKEN14_I2C, CKEN);
266 void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
268 void reset_cpu(ulong ignored)
272 setbits_le32(OWER, OWER_WME);
277 writel(MDREFR_SLFRSH, MDREFR);
283 void enable_caches(void)
285 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
288 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)