1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
14 #include <asm/arch/pxa-regs.h>
16 #include <asm/system.h>
20 static void cache_flush(void)
24 asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
27 int cleanup_before_linux(void)
30 * This function is called just before we call Linux. It prepares
31 * the processor for Linux by just disabling everything that can
32 * disturb booting Linux.
43 inline void writelrb(uint32_t val, uint32_t addr)
46 asm volatile("" : : : "memory");
48 asm volatile("" : : : "memory");
51 void pxa2xx_dram_init(void)
56 * 1) Initialize Asynchronous static memory controller
59 writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
60 writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
61 writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
63 * 2) Initialize Card Interface
66 /* MECR: Memory Expansion Card Register */
67 writelrb(CONFIG_SYS_MECR_VAL, MECR);
68 /* MCMEM0: Card Interface slot 0 timing */
69 writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
70 /* MCMEM1: Card Interface slot 1 timing */
71 writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
72 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
73 writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
74 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
75 writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
76 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
77 writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
78 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
79 writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
82 * 3) Configure Fly-By DMA register
85 writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
88 * 4) Initialize Timing for Sync Memory (SDCLK0)
92 * Before accessing MDREFR we need a valid DRI field, so we set
93 * this to power on defaults + DRI field.
96 /* Read current MDREFR config and zero out DRI */
97 tmp = readl(MDREFR) & ~0xfff;
98 /* Add user-specified DRI */
99 tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
100 /* Configure important bits */
101 tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
102 tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
104 /* Write MDREFR back */
105 writelrb(tmp, MDREFR);
108 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
111 /* Initialize SXCNFG register. Assert the enable bits.
113 * Write SXMRS to cause an MRS command to all enabled banks of
114 * synchronous static memory. Note that SXLCR need not be written
117 writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
120 * 6) Initialize SDRAM
123 writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
124 writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
127 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
128 * but not enable each SDRAM partition pair.
131 writelrb(CONFIG_SYS_MDCNFG_VAL &
132 ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
134 /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
136 while (readl(OSCR) < 0x300)
137 asm volatile("" : : : "memory");
140 * 8) Trigger a number (usually 8) refresh cycles by attempting
141 * non-burst read or write accesses to disabled SDRAM, as commonly
142 * specified in the power up sequence documented in SDRAM data
143 * sheets. The address(es) used for this purpose must not be
146 for (i = 9; i >= 0; i--) {
147 writel(i, 0xa0000000);
148 asm volatile("" : : : "memory");
151 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
154 tmp = CONFIG_SYS_MDCNFG_VAL &
155 (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
156 tmp |= readl(MDCNFG);
157 writelrb(tmp, MDCNFG);
163 writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
169 if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
172 writelrb(tmp, MDREFR);
176 void pxa_gpio_setup(void)
178 writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
179 writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
180 writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
181 #if defined(CONFIG_CPU_PXA27X)
182 writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
185 writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
186 writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
187 writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
188 #if defined(CONFIG_CPU_PXA27X)
189 writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
192 writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
193 writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
194 writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
195 #if defined(CONFIG_CPU_PXA27X)
196 writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
199 writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
200 writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
201 writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
202 writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
203 writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
204 writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
205 #if defined(CONFIG_CPU_PXA27X)
206 writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
207 writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
210 writel(CONFIG_SYS_PSSR_VAL, PSSR);
213 void pxa_interrupt_setup(void)
217 #if defined(CONFIG_CPU_PXA27X)
223 void pxa_clock_setup(void)
225 writel(CONFIG_SYS_CKEN, CKEN);
226 writel(CONFIG_SYS_CCCR, CCCR);
227 asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
229 /* enable the 32Khz oscillator for RTC and PowerManager */
230 writel(OSCC_OON, OSCC);
231 while (!(readl(OSCC) & OSCC_OOK))
232 asm volatile("" : : : "memory");
235 void pxa_wakeup(void)
240 writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
243 if (rcsr & RCSR_SMR) {
244 writel(PSSR_PH, PSSR);
248 asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
252 int arch_cpu_init(void)
256 pxa_interrupt_setup();
261 void i2c_clk_enable(void)
263 /* Set the global I2C clock on */
264 writel(readl(CKEN) | CKEN14_I2C, CKEN);
267 void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
269 void reset_cpu(ulong ignored)
273 setbits_le32(OWER, OWER_WME);
278 writel(MDREFR_SLFRSH, MDREFR);
284 void enable_caches(void)
286 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
289 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)