2 * @file IxNpeDlNpeMgrUtils.c
4 * @author Intel Corporation
5 * @date 18 February 2002
7 * @brief This file contains the implementation of the private API for the
8 * IXP425 NPE Downloader NpeMgr Utils module
12 * IXP400 SW Release version 2.0
14 * -- Copyright Notice --
17 * Copyright 2001-2005, Intel Corporation.
18 * All rights reserved.
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions
24 * 1. Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * 2. Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * 3. Neither the name of the Intel Corporation nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
37 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * -- End of Copyright Notice --
52 * Put the system defined include files required.
54 #define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
60 * Put the user defined include files required.
64 #include "IxNpeDlNpeMgrUtils_p.h"
65 #include "IxNpeDlNpeMgrEcRegisters_p.h"
66 #include "IxNpeDlMacros_p.h"
69 * #defines and macros used in this file.
72 /* used to bit-mask a number of bytes */
73 #define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF
74 #define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF
75 #define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF
77 #define IX_NPEDL_BYTES_PER_WORD 4
78 #define IX_NPEDL_BYTES_PER_SHORT 2
80 #define IX_NPEDL_REG_SIZE_BYTE 8
81 #define IX_NPEDL_REG_SIZE_SHORT 16
82 #define IX_NPEDL_REG_SIZE_WORD 32
85 * Introduce extra read cycles after issuing read command to NPE
86 * so that we read the register after the NPE has updated it
87 * This is to overcome race condition between XScale and NPE
89 #define IX_NPEDL_DELAY_READ_CYCLES 2
91 * To mask top three MSBs of 32bit word to download into NPE IMEM
93 #define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF;
103 } IxNpeDlCtxtRegAccessInfo;
105 /* module statistics counters */
109 UINT32 insMemWriteFails;
110 UINT32 dataMemWrites;
111 UINT32 dataMemWriteFails;
114 UINT32 dbgInstructionExecs;
115 UINT32 contextRegWrites;
116 UINT32 physicalRegWrites;
118 } IxNpeDlNpeMgrUtilsStats;
122 * Variable declarations global to this file only. Externs are followed by
127 * contains useful address and function pointers to read/write Context Regs,
128 * eliminating some switch or if-else statements in places
130 static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] =
133 IX_NPEDL_CTXT_REG_ADDR_STEVT,
134 IX_NPEDL_REG_SIZE_BYTE
137 IX_NPEDL_CTXT_REG_ADDR_STARTPC,
138 IX_NPEDL_REG_SIZE_SHORT
141 IX_NPEDL_CTXT_REG_ADDR_REGMAP,
142 IX_NPEDL_REG_SIZE_SHORT
145 IX_NPEDL_CTXT_REG_ADDR_CINDEX,
146 IX_NPEDL_REG_SIZE_BYTE
150 static UINT32 ixNpeDlSavedExecCount = 0;
151 static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0;
153 static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats;
157 * static function prototypes.
159 PRIVATE __inline__ void
160 ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd,
161 UINT32 addr, UINT32 data);
163 PRIVATE __inline__ UINT32
164 ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr);
167 ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr,
168 UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal);
171 ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
172 UINT32 regVal, UINT32 regSize,
173 UINT32 ctxtNum, BOOL verify);
176 * Function definition: ixNpeDlNpeMgrWriteCommandIssue
178 PRIVATE __inline__ void
179 ixNpeDlNpeMgrWriteCommandIssue (
180 UINT32 npeBaseAddress,
185 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data);
186 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
187 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
192 * Function definition: ixNpeDlNpeMgrReadCommandIssue
194 PRIVATE __inline__ UINT32
195 ixNpeDlNpeMgrReadCommandIssue (
196 UINT32 npeBaseAddress,
203 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
204 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
205 for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++)
207 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data);
214 * Function definition: ixNpeDlNpeMgrInsMemWrite
217 ixNpeDlNpeMgrInsMemWrite (
218 UINT32 npeBaseAddress,
219 UINT32 insMemAddress,
223 UINT32 insMemDataRtn;
225 ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
226 IX_NPEDL_EXCTL_CMD_WR_INS_MEM,
227 insMemAddress, insMemData);
230 /* write invalid data to this reg, so we can see if we're reading
231 the EXDATA register too early */
232 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA,
235 /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/
236 insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
238 insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
239 IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
242 insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
244 if (insMemData != insMemDataRtn)
246 ixNpeDlNpeMgrUtilsStats.insMemWriteFails++;
251 ixNpeDlNpeMgrUtilsStats.insMemWrites++;
257 * Function definition: ixNpeDlNpeMgrDataMemWrite
260 ixNpeDlNpeMgrDataMemWrite (
261 UINT32 npeBaseAddress,
262 UINT32 dataMemAddress,
266 ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
267 IX_NPEDL_EXCTL_CMD_WR_DATA_MEM,
268 dataMemAddress, dataMemData);
271 /* write invalid data to this reg, so we can see if we're reading
272 the EXDATA register too early */
273 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData);
276 ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
277 IX_NPEDL_EXCTL_CMD_RD_DATA_MEM,
280 ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++;
285 ixNpeDlNpeMgrUtilsStats.dataMemWrites++;
291 * Function definition: ixNpeDlNpeMgrExecAccRegWrite
294 ixNpeDlNpeMgrExecAccRegWrite (
295 UINT32 npeBaseAddress,
299 ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
300 IX_NPEDL_EXCTL_CMD_WR_ECS_REG,
301 regAddress, regData);
302 ixNpeDlNpeMgrUtilsStats.ecsRegWrites++;
307 * Function definition: ixNpeDlNpeMgrExecAccRegRead
310 ixNpeDlNpeMgrExecAccRegRead (
311 UINT32 npeBaseAddress,
314 ixNpeDlNpeMgrUtilsStats.ecsRegReads++;
315 return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
316 IX_NPEDL_EXCTL_CMD_RD_ECS_REG,
322 * Function definition: ixNpeDlNpeMgrCommandIssue
325 ixNpeDlNpeMgrCommandIssue (
326 UINT32 npeBaseAddress,
329 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
330 "Entering ixNpeDlNpeMgrCommandIssue\n");
332 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command);
334 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
335 "Exiting ixNpeDlNpeMgrCommandIssue\n");
340 * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec
343 ixNpeDlNpeMgrDebugInstructionPreExec(
344 UINT32 npeBaseAddress)
346 /* turn off the halt bit by clearing Execution Count register. */
347 /* save reg contents 1st and restore later */
348 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
349 &ixNpeDlSavedExecCount);
350 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0);
352 /* ensure that IF and IE are on (temporarily), so that we don't end up
353 * stepping forever */
354 ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
355 IX_NPEDL_ECS_DBG_CTXT_REG_2);
357 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
358 (ixNpeDlSavedEcsDbgCtxtReg2 |
359 IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
360 IX_NPEDL_MASK_ECS_DBG_REG_2_IE));
365 * Function definition: ixNpeDlNpeMgrDebugInstructionExec
368 ixNpeDlNpeMgrDebugInstructionExec(
369 UINT32 npeBaseAddress,
370 UINT32 npeInstruction,
375 UINT32 oldWatchcount, newWatchcount;
376 UINT32 retriesCount = 0;
377 IX_STATUS status = IX_SUCCESS;
379 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
380 "Entering ixNpeDlNpeMgrDebugInstructionExec\n");
382 /* set the Active bit, and the LDUR, in the debug level */
383 ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
384 (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR);
386 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
390 * set CCTXT at ECS DEBUG L3 to specify in which context to execute the
391 * instruction, and set SELCTXT at ECS DEBUG Level to specify which context
393 * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
395 ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) |
396 (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT);
398 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1,
401 /* clear the pipeline */
402 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
404 /* load NPE instruction into the instruction register */
405 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG,
408 /* we need this value later to wait for completion of NPE execution step */
409 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount);
411 /* issue a Step One command via the Execution Control register */
412 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP);
414 /* Watch Count register increments when NPE completes an instruction */
415 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
419 * force the XScale to wait until the NPE has finished execution step
420 * NOTE that this delay will be very small, just long enough to allow a
421 * single NPE instruction to complete execution; if instruction execution
422 * is not completed before timeout retries, exit the while loop
424 while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
425 && (newWatchcount == oldWatchcount))
427 /* Watch Count register increments when NPE completes an instruction */
428 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
434 if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
436 ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++;
440 /* Return timeout status as the instruction has not been executed
441 * after maximum retries */
442 status = IX_NPEDL_CRITICAL_NPE_ERR;
445 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
446 "Exiting ixNpeDlNpeMgrDebugInstructionExec\n");
453 * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec
456 ixNpeDlNpeMgrDebugInstructionPostExec(
457 UINT32 npeBaseAddress)
459 /* clear active bit in debug level */
460 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
463 /* clear the pipeline */
464 ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
466 /* restore Execution Count register contents. */
467 IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
468 ixNpeDlSavedExecCount);
470 /* restore IF and IE bits to original values */
471 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
472 ixNpeDlSavedEcsDbgCtxtReg2);
477 * Function definition: ixNpeDlNpeMgrLogicalRegRead
480 ixNpeDlNpeMgrLogicalRegRead (
481 UINT32 npeBaseAddress,
487 IX_STATUS status = IX_SUCCESS;
488 UINT32 npeInstruction = 0;
491 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
492 "Entering ixNpeDlNpeMgrLogicalRegRead\n");
496 case IX_NPEDL_REG_SIZE_BYTE:
497 npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE;
498 mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
499 case IX_NPEDL_REG_SIZE_SHORT:
500 npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT;
501 mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
502 case IX_NPEDL_REG_SIZE_WORD:
503 npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD;
504 mask = IX_NPEDL_MASK_FULL_WORD; break;
507 /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
508 npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
509 (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
511 /* step execution of NPE intruction using Debug Executing Context stack */
512 status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction,
513 ctxtNum, IX_NPEDL_RD_INSTR_LDUR);
515 if (IX_SUCCESS != status)
520 /* read value of register from Execution Data register */
521 IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal);
523 /* align value from left to right */
524 *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask;
526 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
527 "Exiting ixNpeDlNpeMgrLogicalRegRead\n");
534 * Function definition: ixNpeDlNpeMgrLogicalRegWrite
537 ixNpeDlNpeMgrLogicalRegWrite (
538 UINT32 npeBaseAddress,
545 UINT32 npeInstruction = 0;
547 IX_STATUS status = IX_SUCCESS;
550 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
551 "Entering ixNpeDlNpeMgrLogicalRegWrite\n");
553 if (regSize == IX_NPEDL_REG_SIZE_WORD)
555 /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */
556 /* Write upper half-word (short) to |d0|d1| */
557 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr,
558 regVal >> IX_NPEDL_REG_SIZE_SHORT,
559 IX_NPEDL_REG_SIZE_SHORT,
562 if (IX_SUCCESS != status)
567 /* Write lower half-word (short) to |d2|d3| */
568 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
569 regAddr + IX_NPEDL_BYTES_PER_SHORT,
570 regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD,
571 IX_NPEDL_REG_SIZE_SHORT,
574 if (IX_SUCCESS != status)
583 case IX_NPEDL_REG_SIZE_BYTE:
584 npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
585 mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
586 case IX_NPEDL_REG_SIZE_SHORT:
587 npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT;
588 mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
590 /* mask out any redundant bits, so verify will work later */
593 /* fill dest operand field of instruction with destination reg addr */
594 npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
596 /* fill src operand field of instruction with least-sig 5 bits of val*/
597 npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) <<
598 IX_NPEDL_OFFSET_INSTR_SRC);
600 /* fill coprocessor field of instruction with most-sig 11 bits of val*/
601 npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
602 IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
604 /* step execution of NPE intruction using Debug ECS */
605 status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction,
606 ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
608 if (IX_SUCCESS != status)
612 }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */
616 status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
617 regSize, ctxtNum, &retRegVal);
619 if (IX_SUCCESS == status)
621 if (regVal != retRegVal)
628 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
629 "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n",
637 * Function definition: ixNpeDlNpeMgrPhysicalRegWrite
640 ixNpeDlNpeMgrPhysicalRegWrite (
641 UINT32 npeBaseAddress,
648 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
649 "Entering ixNpeDlNpeMgrPhysicalRegWrite\n");
652 * There are 32 physical registers used in an NPE. These are
653 * treated as 16 pairs of 32-bit registers. To write one of the pair,
654 * write the pair number (0-16) to the REGMAP for Context 0. Then write
655 * the value to register 0 or 4 in the regfile, depending on which
656 * register of the pair is to be written
660 * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
661 * of physical registers to write
663 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
664 IX_NPEDL_CTXT_REG_ADDR_REGMAP,
666 IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
667 IX_NPEDL_REG_SIZE_SHORT, 0, verify);
668 if (status == IX_SUCCESS)
670 /* regAddr = 0 or 4 */
671 regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
672 IX_NPEDL_BYTES_PER_WORD;
674 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue,
675 IX_NPEDL_REG_SIZE_WORD, 0, verify);
678 if (status != IX_SUCCESS)
680 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: "
681 "error writing to physical register\n");
684 ixNpeDlNpeMgrUtilsStats.physicalRegWrites++;
686 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
687 "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n",
694 * Function definition: ixNpeDlNpeMgrCtxtRegWrite
697 ixNpeDlNpeMgrCtxtRegWrite (
698 UINT32 npeBaseAddress,
700 IxNpeDlCtxtRegNum ctxtReg,
707 IX_STATUS status = IX_SUCCESS;
709 IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
710 "Entering ixNpeDlNpeMgrCtxtRegWrite\n");
713 * Context 0 has no STARTPC. Instead, this value is used to set
714 * NextPC for Background ECS, to set where NPE starts executing code
716 if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC))
718 /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */
719 tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
720 IX_NPEDL_ECS_BG_CTXT_REG_0);
721 tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
722 tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) &
723 IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
725 ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress,
726 IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal);
728 ixNpeDlNpeMgrUtilsStats.nextPcWrites++;
732 ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress;
733 ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize;
734 status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr,
735 ctxtRegVal, ctxtRegSize,
737 if (status != IX_SUCCESS)
739 IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: "
740 "error writing to context store register\n");
743 ixNpeDlNpeMgrUtilsStats.contextRegWrites++;
746 IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
747 "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n",
755 * Function definition: ixNpeDlNpeMgrUtilsStatsShow
758 ixNpeDlNpeMgrUtilsStatsShow (void)
760 ixOsalLog (IX_OSAL_LOG_LVL_USER,
761 IX_OSAL_LOG_DEV_STDOUT,
762 "\nixNpeDlNpeMgrUtilsStatsShow:\n"
763 "\tInstruction Memory writes: %u\n"
764 "\tInstruction Memory writes failed: %u\n"
765 "\tData Memory writes: %u\n"
766 "\tData Memory writes failed: %u\n",
767 ixNpeDlNpeMgrUtilsStats.insMemWrites,
768 ixNpeDlNpeMgrUtilsStats.insMemWriteFails,
769 ixNpeDlNpeMgrUtilsStats.dataMemWrites,
770 ixNpeDlNpeMgrUtilsStats.dataMemWriteFails,
773 ixOsalLog (IX_OSAL_LOG_LVL_USER,
774 IX_OSAL_LOG_DEV_STDOUT,
775 "\tExecuting Context Stack Register writes: %u\n"
776 "\tExecuting Context Stack Register reads: %u\n"
777 "\tPhysical Register writes: %u\n"
778 "\tContext Store Register writes: %u\n"
779 "\tExecution Backgound Context NextPC writes: %u\n"
780 "\tDebug Instructions Executed: %u\n\n",
781 ixNpeDlNpeMgrUtilsStats.ecsRegWrites,
782 ixNpeDlNpeMgrUtilsStats.ecsRegReads,
783 ixNpeDlNpeMgrUtilsStats.physicalRegWrites,
784 ixNpeDlNpeMgrUtilsStats.contextRegWrites,
785 ixNpeDlNpeMgrUtilsStats.nextPcWrites,
786 ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs);
791 * Function definition: ixNpeDlNpeMgrUtilsStatsReset
794 ixNpeDlNpeMgrUtilsStatsReset (void)
796 ixNpeDlNpeMgrUtilsStats.insMemWrites = 0;
797 ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0;
798 ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0;
799 ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0;
800 ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0;
801 ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0;
802 ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0;
803 ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0;
804 ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0;
805 ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0;