2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/hardware.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/armv8/mmu.h>
14 #define ZYNQ_SILICON_VER_MASK 0xF000
15 #define ZYNQ_SILICON_VER_SHIFT 12
17 DECLARE_GLOBAL_DATA_PTR;
19 static struct mm_region zynqmp_mem_map[] = {
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
32 PTE_BLOCK_PXN | PTE_BLOCK_UXN
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
41 .virt = 0x400000000UL,
42 .phys = 0x400000000UL,
43 .size = 0x200000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 .virt = 0x600000000UL,
49 .phys = 0x600000000UL,
50 .size = 0x800000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
54 .virt = 0xe00000000UL,
55 .phys = 0xe00000000UL,
56 .size = 0xf200000000UL,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
59 PTE_BLOCK_PXN | PTE_BLOCK_UXN
65 struct mm_region *mem_map = zynqmp_mem_map;
67 u64 get_page_table_size(void)
72 static unsigned int zynqmp_get_silicon_version_secure(void)
76 ver = readl(&csu_base->version);
77 ver &= ZYNQMP_SILICON_VER_MASK;
78 ver >>= ZYNQMP_SILICON_VER_SHIFT;
83 unsigned int zynqmp_get_silicon_version(void)
85 if (current_el() == 3)
86 return zynqmp_get_silicon_version_secure();
88 gd->cpu_clk = get_tbclk();
90 switch (gd->cpu_clk) {
92 return ZYNQMP_CSU_VERSION_VELOCE;
94 return ZYNQMP_CSU_VERSION_QEMU;
96 return ZYNQMP_CSU_VERSION_EP108;
99 return ZYNQMP_CSU_VERSION_SILICON;