1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * David Feng <fenghua@phytium.com.cn>
7 #include <asm-offsets.h>
9 #include <linux/linkage.h>
10 #include <asm/macro.h>
11 #include <asm/armv8/mmu.h>
13 /*************************************************************************
15 * Startup Code (reset vector)
17 *************************************************************************/
21 #if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
22 #include <asm/boot0-linux-kernel-header.h>
23 #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
25 * Various SoCs need something special and SoC-specific up front in
26 * order to boot, allow them to set that in their boot0.h file and then
29 #include <asm/arch/boot0.h>
38 .quad CONFIG_SYS_TEXT_BASE
41 * These are defined in the linker script.
49 .quad __bss_start - _start
53 .quad __bss_end - _start
56 /* Allow the board to save important registers */
58 .globl save_boot_params_ret
61 #if CONFIG_POSITION_INDEPENDENT
63 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
64 * executed at a different address than it was linked at.
67 adr x0, _start /* x0 <- Runtime value of _start */
68 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
69 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
70 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
71 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
73 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
74 ldr x4, [x2], #8 /* x4 <- addend */
75 cmp w1, #1027 /* relative fixup? */
77 /* relative fix: store addend plus offset at dest location */
87 #ifdef CONFIG_SYS_RESET_SCTRL
91 #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
92 .macro set_vbar, regname, reg
97 .macro set_vbar, regname, reg
101 * Could be EL3/EL2/EL1, Initial State:
102 * Little Endian, MMU Disabled, i/dCache Disabled
104 switch_el x1, 3f, 2f, 1f
105 3: set_vbar vbar_el3, x0
107 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
109 msr cptr_el3, xzr /* Enable FP/SIMD */
110 #ifdef COUNTER_FREQUENCY
111 ldr x0, =COUNTER_FREQUENCY
112 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
115 2: set_vbar vbar_el2, x0
117 msr cptr_el2, x0 /* Enable FP/SIMD */
119 1: set_vbar vbar_el1, x0
121 msr cpacr_el1, x0 /* Enable FP/SIMD */
126 * Enable SMPEN bit for coherency.
127 * This register is not architectural but at the moment
128 * this bit should be set for A53/A57/A72.
130 #ifdef CONFIG_ARMV8_SET_SMPEN
131 switch_el x1, 3f, 1f, 1f
133 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
135 msr S3_1_c15_c2_1, x0
140 /* Apply ARM core specific erratas */
144 * Cache/BPB/TLB Invalidate
145 * i-cache is invalidated before enabled in icache_enable()
146 * tlb is invalidated before mmu is enabled in dcache_enable()
147 * d-cache is invalidated before enabled in dcache_enable()
150 /* Processor specific initialization */
153 #if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
154 branch_if_master x0, x1, master_cpu
155 b spin_table_secondary_jump
157 #elif defined(CONFIG_ARMV8_MULTIENTRY)
158 branch_if_master x0, x1, master_cpu
165 ldr x1, =CPU_RELEASE_ADDR
168 br x0 /* branch to the given address */
169 #endif /* CONFIG_ARMV8_MULTIENTRY */
173 #ifdef CONFIG_SYS_RESET_SCTRL
175 switch_el x1, 3f, 2f, 1f
189 switch_el x1, 6f, 5f, 4f
202 b __asm_invalidate_tlb_all
206 /*-----------------------------------------------------------------------*/
208 WEAK(apply_core_errata)
210 mov x29, lr /* Save LR */
211 /* For now, we support Cortex-A53, Cortex-A57 specific errata */
213 /* Check if we are running on a Cortex-A53 core */
214 branch_if_a53_core x0, apply_a53_core_errata
216 /* Check if we are running on a Cortex-A57 core */
217 branch_if_a57_core x0, apply_a57_core_errata
219 mov lr, x29 /* Restore LR */
222 apply_a53_core_errata:
224 #ifdef CONFIG_ARM_ERRATA_855873
234 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
235 /* Enable data cache clean as data cache clean/invalidate */
237 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
242 apply_a57_core_errata:
244 #ifdef CONFIG_ARM_ERRATA_828024
245 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
246 /* Disable non-allocate hint of w-b-n-a memory type */
248 /* Disable write streaming no L1-allocate threshold */
250 /* Disable write streaming no-allocate threshold */
252 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
256 #ifdef CONFIG_ARM_ERRATA_826974
257 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
258 /* Disable speculative load execution ahead of a DMB */
260 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
264 #ifdef CONFIG_ARM_ERRATA_833471
265 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
266 /* FPSCR write flush.
267 * Note that in some cases where a flush is unnecessary this
268 could impact performance. */
270 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
274 #ifdef CONFIG_ARM_ERRATA_829520
275 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
276 /* Disable Indirect Predictor bit will prevent this erratum
278 * Note that in some cases where a flush is unnecessary this
279 could impact performance. */
281 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
285 #ifdef CONFIG_ARM_ERRATA_833069
286 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
287 /* Disable Enable Invalidates of BTB bit */
289 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
293 ENDPROC(apply_core_errata)
295 /*-----------------------------------------------------------------------*/
298 mov x29, lr /* Save LR */
300 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
301 branch_if_slave x0, 1f
305 #if defined(CONFIG_GICV3)
307 bl gic_init_secure_percpu
308 #elif defined(CONFIG_GICV2)
311 bl gic_init_secure_percpu
315 #ifdef CONFIG_ARMV8_MULTIENTRY
316 branch_if_master x0, x1, 2f
319 * Slave should wait for master clearing spin table.
320 * This sync prevent salves observing incorrect
321 * value of spin table and jumping to wrong place.
323 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
327 bl gic_wait_for_interrupt
331 * All slaves will enter EL2 and optionally EL1.
333 adr x4, lowlevel_in_el2
334 ldr x5, =ES_TO_AARCH64
335 bl armv8_switch_to_el2
338 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
339 adr x4, lowlevel_in_el1
340 ldr x5, =ES_TO_AARCH64
341 bl armv8_switch_to_el1
346 #endif /* CONFIG_ARMV8_MULTIENTRY */
349 mov lr, x29 /* Restore LR */
351 ENDPROC(lowlevel_init)
353 WEAK(smp_kick_all_cpus)
354 /* Kick secondary cpus up by SGI 0 interrupt */
355 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
357 b gic_kick_secondary_cpus
360 ENDPROC(smp_kick_all_cpus)
362 /*-----------------------------------------------------------------------*/
364 ENTRY(c_runtime_cpu_setup)
365 #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
368 switch_el x1, 3f, 2f, 1f
378 ENDPROC(c_runtime_cpu_setup)
380 WEAK(save_boot_params)
381 b save_boot_params_ret /* back to my caller */
382 ENDPROC(save_boot_params)