3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/armv8/mmu.h>
14 /*************************************************************************
16 * Startup Code (reset vector)
18 *************************************************************************/
24 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
26 * Various SoCs need something special and SoC-specific up front in
27 * order to boot, allow them to set that in their boot0.h file and then
30 #include <asm/arch/boot0.h>
38 .quad CONFIG_SYS_TEXT_BASE
41 * These are defined in the linker script.
49 .quad __bss_start - _start
53 .quad __bss_end - _start
56 #ifdef CONFIG_SYS_RESET_SCTRL
60 * Could be EL3/EL2/EL1, Initial State:
61 * Little Endian, MMU Disabled, i/dCache Disabled
64 switch_el x1, 3f, 2f, 1f
67 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
69 msr cptr_el3, xzr /* Enable FP/SIMD */
70 #ifdef COUNTER_FREQUENCY
71 ldr x0, =COUNTER_FREQUENCY
72 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
77 msr cptr_el2, x0 /* Enable FP/SIMD */
81 msr cpacr_el1, x0 /* Enable FP/SIMD */
84 /* Enalbe SMPEN bit for coherency.
85 * This register is not architectural but at the moment
86 * this bit should be set for A53/A57/A72.
88 mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
92 /* Apply ARM core specific erratas */
96 * Cache/BPB/TLB Invalidate
97 * i-cache is invalidated before enabled in icache_enable()
98 * tlb is invalidated before mmu is enabled in dcache_enable()
99 * d-cache is invalidated before enabled in dcache_enable()
102 /* Processor specific initialization */
105 #ifdef CONFIG_ARMV8_MULTIENTRY
106 branch_if_master x0, x1, master_cpu
113 ldr x1, =CPU_RELEASE_ADDR
116 br x0 /* branch to the given address */
118 /* On the master CPU */
119 #endif /* CONFIG_ARMV8_MULTIENTRY */
123 #ifdef CONFIG_SYS_RESET_SCTRL
125 switch_el x1, 3f, 2f, 1f
139 switch_el x1, 6f, 5f, 4f
152 b __asm_invalidate_tlb_all
156 /*-----------------------------------------------------------------------*/
158 WEAK(apply_core_errata)
160 mov x29, lr /* Save LR */
161 /* For now, we support Cortex-A57 specific errata only */
163 /* Check if we are running on a Cortex-A57 core */
164 branch_if_a57_core x0, apply_a57_core_errata
166 mov lr, x29 /* Restore LR */
169 apply_a57_core_errata:
171 #ifdef CONFIG_ARM_ERRATA_828024
172 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
173 /* Disable non-allocate hint of w-b-n-a memory type */
175 /* Disable write streaming no L1-allocate threshold */
177 /* Disable write streaming no-allocate threshold */
179 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
182 #ifdef CONFIG_ARM_ERRATA_826974
183 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
184 /* Disable speculative load execution ahead of a DMB */
186 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
189 #ifdef CONFIG_ARM_ERRATA_833471
190 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
191 /* FPSCR write flush.
192 * Note that in some cases where a flush is unnecessary this
193 could impact performance. */
195 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
198 #ifdef CONFIG_ARM_ERRATA_829520
199 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
200 /* Disable Indirect Predictor bit will prevent this erratum
202 * Note that in some cases where a flush is unnecessary this
203 could impact performance. */
205 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
208 #ifdef CONFIG_ARM_ERRATA_833069
209 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
210 /* Disable Enable Invalidates of BTB bit */
212 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
215 ENDPROC(apply_core_errata)
217 /*-----------------------------------------------------------------------*/
220 mov x29, lr /* Save LR */
222 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
223 branch_if_slave x0, 1f
227 #if defined(CONFIG_GICV3)
229 bl gic_init_secure_percpu
230 #elif defined(CONFIG_GICV2)
233 bl gic_init_secure_percpu
237 #ifdef CONFIG_ARMV8_MULTIENTRY
238 branch_if_master x0, x1, 2f
241 * Slave should wait for master clearing spin table.
242 * This sync prevent salves observing incorrect
243 * value of spin table and jumping to wrong place.
245 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
249 bl gic_wait_for_interrupt
253 * All slaves will enter EL2 and optionally EL1.
255 bl armv8_switch_to_el2
256 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
257 bl armv8_switch_to_el1
260 #endif /* CONFIG_ARMV8_MULTIENTRY */
263 mov lr, x29 /* Restore LR */
265 ENDPROC(lowlevel_init)
267 WEAK(smp_kick_all_cpus)
268 /* Kick secondary cpus up by SGI 0 interrupt */
269 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
271 b gic_kick_secondary_cpus
274 ENDPROC(smp_kick_all_cpus)
276 /*-----------------------------------------------------------------------*/
278 ENTRY(c_runtime_cpu_setup)
281 switch_el x1, 3f, 2f, 1f
290 ENDPROC(c_runtime_cpu_setup)