3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/armv8/mmu.h>
14 /*************************************************************************
16 * Startup Code (reset vector)
18 *************************************************************************/
22 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
24 * Various SoCs need something special and SoC-specific up front in
25 * order to boot, allow them to set that in their boot0.h file and then
28 #include <asm/arch/boot0.h>
37 .quad CONFIG_SYS_TEXT_BASE
40 * These are defined in the linker script.
48 .quad __bss_start - _start
52 .quad __bss_end - _start
55 /* Allow the board to save important registers */
57 .globl save_boot_params_ret
60 #if CONFIG_POSITION_INDEPENDENT
62 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
63 * executed at a different address than it was linked at.
66 adr x0, _start /* x0 <- Runtime value of _start */
67 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
68 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
69 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
70 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
72 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
73 ldr x4, [x2], #8 /* x4 <- addend */
74 cmp w1, #1027 /* relative fixup? */
76 /* relative fix: store addend plus offset at dest location */
86 #ifdef CONFIG_SYS_RESET_SCTRL
90 * Could be EL3/EL2/EL1, Initial State:
91 * Little Endian, MMU Disabled, i/dCache Disabled
94 switch_el x1, 3f, 2f, 1f
97 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
99 msr cptr_el3, xzr /* Enable FP/SIMD */
100 #ifdef COUNTER_FREQUENCY
101 ldr x0, =COUNTER_FREQUENCY
102 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
107 msr cptr_el2, x0 /* Enable FP/SIMD */
111 msr cpacr_el1, x0 /* Enable FP/SIMD */
115 * Enable SMPEN bit for coherency.
116 * This register is not architectural but at the moment
117 * this bit should be set for A53/A57/A72.
119 #ifdef CONFIG_ARMV8_SET_SMPEN
120 switch_el x1, 3f, 1f, 1f
122 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
124 msr S3_1_c15_c2_1, x0
128 /* Apply ARM core specific erratas */
132 * Cache/BPB/TLB Invalidate
133 * i-cache is invalidated before enabled in icache_enable()
134 * tlb is invalidated before mmu is enabled in dcache_enable()
135 * d-cache is invalidated before enabled in dcache_enable()
138 /* Processor specific initialization */
141 #if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
142 branch_if_master x0, x1, master_cpu
143 b spin_table_secondary_jump
145 #elif defined(CONFIG_ARMV8_MULTIENTRY)
146 branch_if_master x0, x1, master_cpu
153 ldr x1, =CPU_RELEASE_ADDR
156 br x0 /* branch to the given address */
157 #endif /* CONFIG_ARMV8_MULTIENTRY */
161 #ifdef CONFIG_SYS_RESET_SCTRL
163 switch_el x1, 3f, 2f, 1f
177 switch_el x1, 6f, 5f, 4f
190 b __asm_invalidate_tlb_all
194 /*-----------------------------------------------------------------------*/
196 WEAK(apply_core_errata)
198 mov x29, lr /* Save LR */
199 /* For now, we support Cortex-A57 specific errata only */
201 /* Check if we are running on a Cortex-A57 core */
202 branch_if_a57_core x0, apply_a57_core_errata
204 mov lr, x29 /* Restore LR */
207 apply_a57_core_errata:
209 #ifdef CONFIG_ARM_ERRATA_828024
210 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
211 /* Disable non-allocate hint of w-b-n-a memory type */
213 /* Disable write streaming no L1-allocate threshold */
215 /* Disable write streaming no-allocate threshold */
217 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
220 #ifdef CONFIG_ARM_ERRATA_826974
221 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
222 /* Disable speculative load execution ahead of a DMB */
224 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
227 #ifdef CONFIG_ARM_ERRATA_833471
228 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
229 /* FPSCR write flush.
230 * Note that in some cases where a flush is unnecessary this
231 could impact performance. */
233 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
236 #ifdef CONFIG_ARM_ERRATA_829520
237 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
238 /* Disable Indirect Predictor bit will prevent this erratum
240 * Note that in some cases where a flush is unnecessary this
241 could impact performance. */
243 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
246 #ifdef CONFIG_ARM_ERRATA_833069
247 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
248 /* Disable Enable Invalidates of BTB bit */
250 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
253 ENDPROC(apply_core_errata)
255 /*-----------------------------------------------------------------------*/
258 mov x29, lr /* Save LR */
260 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
261 branch_if_slave x0, 1f
265 #if defined(CONFIG_GICV3)
267 bl gic_init_secure_percpu
268 #elif defined(CONFIG_GICV2)
271 bl gic_init_secure_percpu
275 #ifdef CONFIG_ARMV8_MULTIENTRY
276 branch_if_master x0, x1, 2f
279 * Slave should wait for master clearing spin table.
280 * This sync prevent salves observing incorrect
281 * value of spin table and jumping to wrong place.
283 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
287 bl gic_wait_for_interrupt
291 * All slaves will enter EL2 and optionally EL1.
293 adr x4, lowlevel_in_el2
294 ldr x5, =ES_TO_AARCH64
295 bl armv8_switch_to_el2
298 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
299 adr x4, lowlevel_in_el1
300 ldr x5, =ES_TO_AARCH64
301 bl armv8_switch_to_el1
306 #endif /* CONFIG_ARMV8_MULTIENTRY */
309 mov lr, x29 /* Restore LR */
311 ENDPROC(lowlevel_init)
313 WEAK(smp_kick_all_cpus)
314 /* Kick secondary cpus up by SGI 0 interrupt */
315 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
317 b gic_kick_secondary_cpus
320 ENDPROC(smp_kick_all_cpus)
322 /*-----------------------------------------------------------------------*/
324 ENTRY(c_runtime_cpu_setup)
327 switch_el x1, 3f, 2f, 1f
336 ENDPROC(c_runtime_cpu_setup)
338 WEAK(save_boot_params)
339 b save_boot_params_ret /* back to my caller */
340 ENDPROC(save_boot_params)