1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
7 #include <clock_legacy.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/mc_cgm_regs.h>
15 #include <asm/arch/mc_me_regs.h>
16 #include <asm/arch/mc_rgm_regs.h>
23 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
24 u32 cpu = readl(&mscmir->cpxtype);
29 DECLARE_GLOBAL_DATA_PTR;
31 static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
32 u32 pllfd, u32 selected_output)
34 u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
35 u32 plldv_rfdphi_div = 0, fout = 0;
36 u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
38 if (selected_output > DFS_MAXNUMBER) {
43 (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
44 plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
46 pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
48 plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
50 /* The formula for VCO is from TR manual, rev. D */
51 vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
53 if (selected_output != 0) {
54 /* Determine the RFDPHI for PHI1 */
56 (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
57 PLLDIG_PLLDV_RFDPHI1_OFFSET;
58 plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
59 if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
61 readl(DFS_DVPORTn(pll, selected_output - 1));
63 (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
64 DFS_DVPORTn_MFI_OFFSET;
66 (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
67 DFS_DVPORTn_MFI_OFFSET;
68 fout = vco / (dfs_mfi + (dfs_mfn / 256));
70 fout = vco / plldv_rfdphi_div;
74 /* Determine the RFDPHI for PHI0 */
76 (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
77 PLLDIG_PLLDV_RFDPHI_OFFSET;
78 fout = vco / plldv_rfdphi_div;
85 /* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
86 static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
91 plldv = readl(PLLDIG_PLLDV(pll));
92 pllfd = readl(PLLDIG_PLLFD(pll));
94 return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
97 static u32 get_mcu_main_clk(void)
103 sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
104 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
107 readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
108 coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
111 switch (sysclk_sel) {
112 case MC_CGM_SC_SEL_FIRC:
113 freq = FIRC_CLK_FREQ;
115 case MC_CGM_SC_SEL_XOSC:
116 freq = XOSC_CLK_FREQ;
118 case MC_CGM_SC_SEL_ARMPLL:
119 /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
120 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
122 case MC_CGM_SC_SEL_CLKDISABLE:
123 printf("Sysclk is disabled\n");
126 printf("unsupported system clock select\n");
129 return freq / coreclk_div;
132 static u32 get_sys_clk(u32 number)
134 u32 sysclk_div, sysclk_div_number;
140 sysclk_div_number = 0;
143 sysclk_div_number = 1;
146 printf("unsupported system clock \n");
149 sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
150 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
153 readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
154 MC_CGM_SC_DCn_PREDIV_MASK;
155 sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
158 switch (sysclk_sel) {
159 case MC_CGM_SC_SEL_FIRC:
160 freq = FIRC_CLK_FREQ;
162 case MC_CGM_SC_SEL_XOSC:
163 freq = XOSC_CLK_FREQ;
165 case MC_CGM_SC_SEL_ARMPLL:
166 /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
167 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
169 case MC_CGM_SC_SEL_CLKDISABLE:
170 printf("Sysclk is disabled\n");
173 printf("unsupported system clock select\n");
176 return freq / sysclk_div;
179 static u32 get_peripherals_clk(void)
185 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
186 MC_CGM_ACn_DCm_PREDIV_MASK;
187 aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
190 freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
192 return freq / aux5clk_div;
196 static u32 get_uart_clk(void)
198 u32 auxclk3_div, auxclk3_sel, freq = 0;
201 readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
202 auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
205 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
206 MC_CGM_ACn_DCm_PREDIV_MASK;
207 auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
210 switch (auxclk3_sel) {
211 case MC_CGM_ACn_SEL_FIRC:
212 freq = FIRC_CLK_FREQ;
214 case MC_CGM_ACn_SEL_XOSC:
215 freq = XOSC_CLK_FREQ;
217 case MC_CGM_ACn_SEL_PERPLLDIVX:
218 freq = get_peripherals_clk() / 3;
220 case MC_CGM_ACn_SEL_SYSCLK:
221 freq = get_sys_clk(6);
224 printf("unsupported system clock select\n");
227 return freq / auxclk3_div;
230 static u32 get_fec_clk(void)
236 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
237 MC_CGM_ACn_DCm_PREDIV_MASK;
238 aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
241 freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
243 return freq / aux2clk_div;
246 static u32 get_usdhc_clk(void)
252 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
253 MC_CGM_ACn_DCm_PREDIV_MASK;
254 aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
257 freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
259 return freq / aux15clk_div;
262 static u32 get_i2c_clk(void)
264 return get_peripherals_clk();
267 /* return clocks in Hz */
268 unsigned int mxc_get_clock(enum mxc_clock clk)
272 return get_mcu_main_clk();
273 case MXC_PERIPHERALS_CLK:
274 return get_peripherals_clk();
276 return get_uart_clk();
278 return get_fec_clk();
280 return get_i2c_clk();
282 return get_usdhc_clk();
286 printf("Error: Unsupported function to read the frequency! \
287 Please define it correctly!");
291 /* Not yet implemented - int soc_clk_dump(); */
293 #if defined(CONFIG_DISPLAY_CPUINFO)
294 static char *get_reset_cause(void)
296 u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
304 return "FCCU soft reaction";
306 return "FCCU hard reaction";
308 return "Software Functional reset";
310 return "Self Test done reset";
312 return "External reset";
314 return "unknown reset";
319 #define SRC_SCR_SW_RST (1<<12)
321 void reset_cpu(ulong addr)
323 printf("Feature not supported.\n");
326 int print_cpuinfo(void)
328 printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
329 mxc_get_clock(MXC_ARM_CLK) / 1000000);
330 printf("Reset cause: %s\n", get_reset_cause());
336 int cpu_eth_init(bd_t * bis)
340 #if defined(CONFIG_FEC_MXC)
341 rc = fecmxc_initialize(bis);
349 #ifdef CONFIG_FSL_ESDHC_IMX
350 gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);