2 # Copyright 2014 Freescale Semiconductor
4 # SPDX-License-Identifier: GPL-2.0+
7 Freescale LayerScape with Chassis Generation 3
9 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
15 (1) A typical layout of various images (including Linux and other firmware images)
16 is shown below considering a 32MB NOR flash device present on most
17 pre-silicon platforms (simulator and emulator):
19 -------------------------
21 | (linux + DTB + RFS) |
22 ------------------------- ----> 0x0120_0000
24 ------------------------- ----> 0x00C0_0000
26 ------------------------- ----> 0x0070_0000
28 ------------------------- ----> 0x006C_0000
30 ------------------------- ----> 0x0020_0000
32 ------------------------- ----> 0x0000_1000
34 ------------------------- ----> 0x0000_0080
36 ------------------------- ----> 0x0000_0000
38 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
40 (2) A typical layout of various images (including Linux and other firmware images)
41 is shown below considering a 128MB NOR flash device present on QDS and RDB
43 ----------------------------------------- ----> 0x5_8800_0000 ---
44 | .. Unused .. (7M) | |
45 ----------------------------------------- ----> 0x5_8790_0000 |
46 | FIT Image (linux + DTB + RFS) (40M) | |
47 ----------------------------------------- ----> 0x5_8510_0000 |
48 | PHY firmware (2M) | |
49 ----------------------------------------- ----> 0x5_84F0_0000 | 64K
50 | Debug Server FW (2M) | | Alt
51 ----------------------------------------- ----> 0x5_84D0_0000 | Bank
53 ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
54 | MC DPC Blob (1M) | |
55 ----------------------------------------- ----> 0x5_8480_0000 |
56 | MC DPL Blob (1M) | |
57 ----------------------------------------- ----> 0x5_8470_0000 |
59 ----------------------------------------- ----> 0x5_8430_0000 |
60 | BootLoader Environment (1M) | |
61 ----------------------------------------- ----> 0x5_8420_0000 |
63 ----------------------------------------- ----> 0x5_8410_0000 |
64 | RCW and PBI (1M) | |
65 ----------------------------------------- ----> 0x5_8400_0000 ---
66 | .. Unused .. (7M) | |
67 ----------------------------------------- ----> 0x5_8390_0000 |
68 | FIT Image (linux + DTB + RFS) (40M) | |
69 ----------------------------------------- ----> 0x5_8110_0000 |
70 | PHY firmware (2M) | |
71 ----------------------------------------- ----> 0x5_80F0_0000 | 64K
72 | Debug Server FW (2M) | | Bank
73 ----------------------------------------- ----> 0x5_80D0_0000 |
75 ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
76 | MC DPC Blob (1M) | |
77 ----------------------------------------- ----> 0x5_8080_0000 |
78 | MC DPL Blob (1M) | |
79 ----------------------------------------- ----> 0x5_8070_0000 |
81 ----------------------------------------- ----> 0x5_8030_0000 |
82 | BootLoader Environment (1M) | |
83 ----------------------------------------- ----> 0x5_8020_0000 |
85 ----------------------------------------- ----> 0x5_8010_0000 |
86 | RCW and PBI (1M) | |
87 ----------------------------------------- ----> 0x5_8000_0000 ---
89 128-MB NOR flash layout for QDS and RDB boards
93 mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
94 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
96 mcmemsize: MC DRAM block size. If this variable is not defined, the value
97 CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
101 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
102 The difference between NAND boot RCW image and NOR boot image is the PBI
103 command sequence. Below is one example for PBI commands for QDS which uses
104 NAND device with 2KB/page, block size 128KB.
106 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
107 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
108 The above two commands set bootloc register to 0x00000000_1800a000 where
109 the u-boot code will be running in OCRAM.
111 3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
112 BLOCK_SIZE=0x00014000
113 This command copies u-boot image from NAND device into OCRAM. The values need
114 to adjust accordingly.
116 SRC should match the cfg_rcw_src, the reset config pins. It depends
117 on the NAND device. See reference manual for cfg_rcw_src.
118 SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
119 the example above, 128KB. For easy maintenance, we put it at
120 the beginning of next block from RCW.
121 DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
122 BLOCK_SIZE is the size to be copied by PBI.
124 RCW image should be written to the beginning of NAND device. Example of using
127 nand write <rcw image in memory> 0 <size of rcw image>
129 To form the NAND image, build u-boot with NAND config, for example,
130 ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
131 The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
133 nand write <u-boot image in memory> 200000 <size of u-boot image>
135 With these two images in NAND device, the board can boot from NAND.