2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/soc.h>
15 #include <asm/global_data.h>
16 #include <asm/arch-fsl-layerscape/config.h>
17 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
20 #ifdef CONFIG_SYS_FSL_DDR
21 #include <fsl_ddr_sdram.h>
24 #ifdef CONFIG_CHAIN_OF_TRUST
25 #include <fsl_validate.h>
27 #include <fsl_immap.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 bool soc_has_dp_ddr(void)
33 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
34 u32 svr = gur_in32(&gur->svr);
36 /* LS2085A, LS2088A, LS2048A has DP_DDR */
37 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
38 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
39 (SVR_SOC_VER(svr) == SVR_LS2048A))
45 bool soc_has_aiop(void)
47 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
48 u32 svr = gur_in32(&gur->svr);
50 /* LS2085A has AIOP */
51 if (SVR_SOC_VER(svr) == SVR_LS2085A)
57 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
59 scfg_clrsetbits32(scfg + offset / 4,
61 SCFG_USB_TXVREFTUNE << 6);
64 static void erratum_a009008(void)
66 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
67 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
69 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
70 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
71 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
72 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
73 #elif defined(CONFIG_ARCH_LS2080A)
74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
76 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
79 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
81 scfg_clrbits32(scfg + offset / 4,
82 SCFG_USB_SQRXTUNE_MASK << 23);
85 static void erratum_a009798(void)
87 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
88 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
90 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
91 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
92 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
93 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
94 #elif defined(CONFIG_ARCH_LS2080A)
95 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
97 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
100 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
101 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
103 scfg_clrsetbits32(scfg + offset / 4,
105 SCFG_USB_PCSTXSWINGFULL << 9);
109 static void erratum_a008997(void)
111 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
112 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
113 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
115 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
116 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
117 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
119 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
122 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
124 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
125 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
126 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
127 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
128 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
130 #elif defined(CONFIG_ARCH_LS2080A)
132 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
133 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
134 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
135 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
136 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
140 static void erratum_a009007(void)
142 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
143 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
145 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
147 usb_phy = (void __iomem *)SCFG_USB_PHY2;
148 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
150 usb_phy = (void __iomem *)SCFG_USB_PHY3;
151 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
152 #elif defined(CONFIG_ARCH_LS2080A)
153 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
155 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
156 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
157 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
160 #if defined(CONFIG_FSL_LSCH3)
162 * This erratum requires setting a value to eddrtqcr1 to
163 * optimal the DDR performance.
165 static void erratum_a008336(void)
167 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
170 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
171 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
172 if (fsl_ddr_get_version(0) == 0x50200)
173 out_le32(eddrtqcr1, 0x63b30002);
175 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
176 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
177 if (fsl_ddr_get_version(0) == 0x50200)
178 out_le32(eddrtqcr1, 0x63b30002);
184 * This erratum requires a register write before being Memory
185 * controller 3 being enabled.
187 static void erratum_a008514(void)
189 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
192 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
193 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
194 out_le32(eddrtqcr1, 0x63b20002);
198 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
199 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
201 static unsigned long get_internval_val_mhz(void)
203 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
205 * interval is the number of platform cycles(MHz) between
206 * wake up events generated by EPU.
208 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
211 interval_mhz = simple_strtoul(interval, NULL, 10);
216 void erratum_a009635(void)
219 unsigned long interval_mhz = get_internval_val_mhz();
224 val = in_le32(DCSR_CGACRE5);
225 writel(val | 0x00000200, DCSR_CGACRE5);
227 val = in_le32(EPU_EPCMPR5);
228 writel(interval_mhz, EPU_EPCMPR5);
229 val = in_le32(EPU_EPCCR5);
230 writel(val | 0x82820000, EPU_EPCCR5);
231 val = in_le32(EPU_EPSMCR5);
232 writel(val | 0x002f0000, EPU_EPSMCR5);
233 val = in_le32(EPU_EPECR5);
234 writel(val | 0x20000000, EPU_EPECR5);
235 val = in_le32(EPU_EPGCR);
236 writel(val | 0x80000000, EPU_EPGCR);
238 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
240 static void erratum_rcw_src(void)
242 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
243 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
244 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
247 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
248 val &= ~DCFG_PORSR1_RCW_SRC;
249 val |= DCFG_PORSR1_RCW_SRC_NOR;
250 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
254 #define I2C_DEBUG_REG 0x6
255 #define I2C_GLITCH_EN 0x8
257 * This erratum requires setting glitch_en bit to enable
258 * digital glitch filter to improve clock stability.
260 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
261 static void erratum_a009203(void)
264 #ifdef CONFIG_SYS_I2C
265 #ifdef I2C1_BASE_ADDR
266 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
268 writeb(I2C_GLITCH_EN, ptr);
270 #ifdef I2C2_BASE_ADDR
271 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
273 writeb(I2C_GLITCH_EN, ptr);
275 #ifdef I2C3_BASE_ADDR
276 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
278 writeb(I2C_GLITCH_EN, ptr);
280 #ifdef I2C4_BASE_ADDR
281 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
283 writeb(I2C_GLITCH_EN, ptr);
289 void bypass_smmu(void)
292 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
293 out_le32(SMMU_SCR0, val);
294 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
295 out_le32(SMMU_NSCR0, val);
297 void fsl_lsch3_early_init_f(void)
300 init_early_memctl_regs(); /* tighten IFC timing */
301 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
310 #ifdef CONFIG_CHAIN_OF_TRUST
311 /* In case of Secure Boot, the IBR configures the SMMU
312 * to allow only Secure transactions.
313 * SMMU must be reset in bypass mode.
314 * Set the ClientPD bit and Clear the USFCFG Bit
316 if (fsl_check_boot_mode_secure() == 1)
321 #ifdef CONFIG_SCSI_AHCI_PLAT
324 struct ccsr_ahci __iomem *ccsr_ahci;
326 #ifdef CONFIG_SYS_SATA2
327 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
328 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
329 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
330 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
333 #ifdef CONFIG_SYS_SATA1
334 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
335 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
336 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
337 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
339 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
347 #elif defined(CONFIG_FSL_LSCH2)
348 #ifdef CONFIG_SCSI_AHCI_PLAT
351 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
353 /* Disable SATA ECC */
354 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
355 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
356 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
357 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
359 ahci_init((void __iomem *)CONFIG_SYS_SATA);
366 static void erratum_a009929(void)
368 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
369 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
370 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
371 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
373 rstrqmr1 |= 0x00000400;
374 gur_out32(&gur->rstrqmr1, rstrqmr1);
375 writel(0x01000000, dcsr_cop_ccp);
380 * This erratum requires setting a value to eddrtqcr1 to optimal
381 * the DDR performance. The eddrtqcr1 register is in SCFG space
382 * of LS1043A and the offset is 0x157_020c.
384 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
385 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
386 #error A009660 and A008514 can not be both enabled.
389 static void erratum_a009660(void)
391 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
392 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
393 out_be32(eddrtqcr1, 0x63b20042);
397 static void erratum_a008850_early(void)
399 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
401 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
402 CONFIG_SYS_CCI400_OFFSET);
403 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
405 /* Skip if running at lower exception level */
406 if (current_el() < 3)
409 /* disables propagation of barrier transactions to DDRC from CCI400 */
410 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
412 /* disable the re-ordering in DDRC */
413 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
417 void erratum_a008850_post(void)
419 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
421 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
422 CONFIG_SYS_CCI400_OFFSET);
423 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
426 /* Skip if running at lower exception level */
427 if (current_el() < 3)
430 /* enable propagation of barrier transactions to DDRC from CCI400 */
431 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
433 /* enable the re-ordering in DDRC */
434 tmp = ddr_in32(&ddr->eor);
435 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
436 ddr_out32(&ddr->eor, tmp);
440 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
441 void erratum_a010315(void)
445 for (i = PCIE1; i <= PCIE4; i++)
446 if (!is_serdes_configured(i)) {
447 debug("PCIe%d: disabled all R/W permission!\n", i);
448 set_pcie_ns_access(i, 0);
453 static void erratum_a010539(void)
455 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
456 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
459 porsr1 = in_be32(&gur->porsr1);
460 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
461 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
466 /* Get VDD in the unit mV from voltage ID */
467 int get_core_volt_from_fuse(void)
469 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
474 fusesr = in_be32(&gur->dcfg_fusesr);
475 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
476 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
477 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
478 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
479 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
480 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
482 debug("%s: VID = 0x%x\n", __func__, vid);
484 case 0x00: /* VID isn't supported */
486 debug("%s: The VID feature is not supported\n", __func__);
488 case 0x08: /* 0.9V silicon */
491 case 0x10: /* 1.0V silicon */
494 default: /* Other core voltage */
496 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
499 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
504 __weak int board_switch_core_volt(u32 vdd)
509 static int setup_core_volt(u32 vdd)
511 return board_setup_core_volt(vdd);
514 #ifdef CONFIG_SYS_FSL_DDR
515 static void ddr_enable_0v9_volt(bool en)
517 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
520 tmp = ddr_in32(&ddr->ddr_cdr1);
523 tmp |= DDR_CDR1_V0PT9_EN;
525 tmp &= ~DDR_CDR1_V0PT9_EN;
527 ddr_out32(&ddr->ddr_cdr1, tmp);
531 int setup_chip_volt(void)
535 vdd = get_core_volt_from_fuse();
536 /* Nothing to do for silicons doesn't support VID */
540 if (setup_core_volt(vdd))
541 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
542 #ifdef CONFIG_SYS_HAS_SERDES
543 if (setup_serdes_volt(vdd))
544 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
547 #ifdef CONFIG_SYS_FSL_DDR
549 ddr_enable_0v9_volt(true);
555 void fsl_lsch2_early_init_f(void)
557 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
558 CONFIG_SYS_CCI400_OFFSET);
559 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
561 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
562 enable_layerscape_ns_access();
565 #ifdef CONFIG_FSL_IFC
566 init_early_memctl_regs(); /* tighten IFC timing */
569 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
570 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
572 /* Make SEC reads and writes snoopable */
573 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
574 SCFG_SNPCNFGCR_SECWRSNP |
575 SCFG_SNPCNFGCR_SATARDSNP |
576 SCFG_SNPCNFGCR_SATAWRSNP);
579 * Enable snoop requests and DVM message requests for
580 * Slave insterface S4 (A53 core cluster)
582 if (current_el() == 3) {
583 out_le32(&cci->slave[4].snoop_ctrl,
584 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
588 erratum_a008850_early(); /* part 1 of 2 */
599 #ifdef CONFIG_QSPI_AHB_INIT
600 /* Enable 4bytes address support and fast read */
601 int qspi_ahb_init(void)
603 u32 *qspi_lut, lut_key, *qspi_key;
605 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
606 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
608 lut_key = in_be32(qspi_key);
610 if (lut_key == 0x5af05af0) {
611 /* That means the register is BE */
612 out_be32(qspi_key, 0x5af05af0);
613 /* Unlock the lut table */
614 out_be32(qspi_key + 1, 0x00000002);
615 out_be32(qspi_lut, 0x0820040c);
616 out_be32(qspi_lut + 1, 0x1c080c08);
617 out_be32(qspi_lut + 2, 0x00002400);
618 /* Lock the lut table */
619 out_be32(qspi_key, 0x5af05af0);
620 out_be32(qspi_key + 1, 0x00000001);
622 /* That means the register is LE */
623 out_le32(qspi_key, 0x5af05af0);
624 /* Unlock the lut table */
625 out_le32(qspi_key + 1, 0x00000002);
626 out_le32(qspi_lut, 0x0820040c);
627 out_le32(qspi_lut + 1, 0x1c080c08);
628 out_le32(qspi_lut + 2, 0x00002400);
629 /* Lock the lut table */
630 out_le32(qspi_key, 0x5af05af0);
631 out_le32(qspi_key + 1, 0x00000001);
638 #ifdef CONFIG_BOARD_LATE_INIT
639 int board_late_init(void)
641 #ifdef CONFIG_SCSI_AHCI_PLAT
644 #ifdef CONFIG_CHAIN_OF_TRUST
645 fsl_setenv_chain_of_trust();
647 #ifdef CONFIG_QSPI_AHB_INIT