1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
4 * Copyright 2019-2021 NXP
8 #include <clock_legacy.h>
11 #include <fsl_immap.h>
14 #include <linux/sizes.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/soc.h>
18 #include <asm/cache.h>
20 #include <asm/global_data.h>
21 #include <asm/arch-fsl-layerscape/config.h>
22 #include <asm/arch-fsl-layerscape/ns_access.h>
23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
24 #include <asm/gic-v3.h>
25 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
28 #ifdef CONFIG_SYS_FSL_DDR
29 #include <fsl_ddr_sdram.h>
32 #ifdef CONFIG_CHAIN_OF_TRUST
33 #include <fsl_validate.h>
35 #include <fsl_immap.h>
37 #include <dm/device_compat.h>
38 #include <linux/err.h>
39 #ifdef CONFIG_GIC_V3_ITS
40 DECLARE_GLOBAL_DATA_PTR;
43 #ifdef CONFIG_GIC_V3_ITS
44 #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
45 #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
46 #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
47 PROPTABLE_MAX_SZ, SZ_1M)
48 static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
51 struct fdt_memory gic_rd_tables;
53 gic_rd_tables.start = base;
54 gic_rd_tables.end = base + size - 1;
55 err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
58 debug("%s: failed to add reserved memory: %d\n", __func__, err);
63 int ls_gic_rd_tables_init(void *blob)
68 gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
69 ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
73 ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
75 debug("%s: failed to init gic-lpi-tables\n", __func__);
81 bool soc_has_dp_ddr(void)
83 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
84 u32 svr = gur_in32(&gur->svr);
86 /* LS2085A, LS2088A, LS2048A has DP_DDR */
87 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
88 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
89 (SVR_SOC_VER(svr) == SVR_LS2048A))
95 bool soc_has_aiop(void)
97 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
98 u32 svr = gur_in32(&gur->svr);
100 /* LS2085A has AIOP */
101 if (SVR_SOC_VER(svr) == SVR_LS2085A)
107 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
109 scfg_clrsetbits32(scfg + offset / 4,
111 SCFG_USB_TXVREFTUNE << 6);
114 static void erratum_a009008(void)
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
117 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
119 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
120 defined(CONFIG_ARCH_LS1012A)
121 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
122 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
123 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
124 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
126 #elif defined(CONFIG_ARCH_LS2080A)
127 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
129 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
132 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
134 scfg_clrbits32(scfg + offset / 4,
135 SCFG_USB_SQRXTUNE_MASK << 23);
138 static void erratum_a009798(void)
140 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
141 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
143 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
144 defined(CONFIG_ARCH_LS1012A)
145 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
146 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
147 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
148 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
150 #elif defined(CONFIG_ARCH_LS2080A)
151 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
153 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
156 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
157 defined(CONFIG_ARCH_LS1012A)
158 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
160 scfg_clrsetbits32(scfg + offset / 4,
162 SCFG_USB_PCSTXSWINGFULL << 9);
166 static void erratum_a008997(void)
168 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
169 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
170 defined(CONFIG_ARCH_LS1012A)
171 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
173 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
174 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
175 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
176 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
178 #elif defined(CONFIG_ARCH_LS1028A)
179 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
181 DCSR_USB_PCSTXSWINGFULL << 11);
183 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
186 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
187 defined(CONFIG_ARCH_LS1012A)
189 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
190 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
191 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
192 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
193 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
195 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
196 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
197 defined(CONFIG_ARCH_LX2162A)
199 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
200 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
201 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
202 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
203 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
207 static void erratum_a009007(void)
209 if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007))
212 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
213 defined(CONFIG_ARCH_LS1012A)
214 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
216 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
217 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
218 usb_phy = (void __iomem *)SCFG_USB_PHY2;
219 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
221 usb_phy = (void __iomem *)SCFG_USB_PHY3;
222 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
224 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
225 defined(CONFIG_ARCH_LS1028A)
226 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
228 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
229 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
230 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
233 #if defined(CONFIG_FSL_LSCH3)
234 static void erratum_a050204(void)
236 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
237 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
239 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
240 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
244 * This erratum requires setting a value to eddrtqcr1 to
245 * optimal the DDR performance.
247 static void erratum_a008336(void)
249 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
252 #ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
253 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
254 if (fsl_ddr_get_version(0) == 0x50200)
255 out_le32(eddrtqcr1, 0x63b30002);
257 #ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
258 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
259 if (fsl_ddr_get_version(0) == 0x50200)
260 out_le32(eddrtqcr1, 0x63b30002);
266 * This erratum requires a register write before being Memory
267 * controller 3 being enabled.
269 static void erratum_a008514(void)
271 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
274 #ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
275 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
276 out_le32(eddrtqcr1, 0x63b20002);
280 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
281 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
283 static unsigned long get_internval_val_mhz(void)
285 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
287 * interval is the number of platform cycles(MHz) between
288 * wake up events generated by EPU.
290 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
293 interval_mhz = dectoul(interval, NULL);
298 void erratum_a009635(void)
301 unsigned long interval_mhz = get_internval_val_mhz();
306 val = in_le32(DCSR_CGACRE5);
307 writel(val | 0x00000200, DCSR_CGACRE5);
309 val = in_le32(EPU_EPCMPR5);
310 writel(interval_mhz, EPU_EPCMPR5);
311 val = in_le32(EPU_EPCCR5);
312 writel(val | 0x82820000, EPU_EPCCR5);
313 val = in_le32(EPU_EPSMCR5);
314 writel(val | 0x002f0000, EPU_EPSMCR5);
315 val = in_le32(EPU_EPECR5);
316 writel(val | 0x20000000, EPU_EPECR5);
317 val = in_le32(EPU_EPGCR);
318 writel(val | 0x80000000, EPU_EPGCR);
320 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
322 static void erratum_rcw_src(void)
324 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
325 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
326 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
329 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
330 val &= ~DCFG_PORSR1_RCW_SRC;
331 val |= DCFG_PORSR1_RCW_SRC_NOR;
332 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
336 #define I2C_DEBUG_REG 0x6
337 #define I2C_GLITCH_EN 0x8
339 * This erratum requires setting glitch_en bit to enable
340 * digital glitch filter to improve clock stability.
342 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
343 static void erratum_a009203(void)
345 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
347 #ifdef I2C1_BASE_ADDR
348 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
350 writeb(I2C_GLITCH_EN, ptr);
352 #ifdef I2C2_BASE_ADDR
353 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
355 writeb(I2C_GLITCH_EN, ptr);
357 #ifdef I2C3_BASE_ADDR
358 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
360 writeb(I2C_GLITCH_EN, ptr);
362 #ifdef I2C4_BASE_ADDR
363 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
365 writeb(I2C_GLITCH_EN, ptr);
371 void bypass_smmu(void)
374 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
375 out_le32(SMMU_SCR0, val);
376 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
377 out_le32(SMMU_NSCR0, val);
379 void fsl_lsch3_early_init_f(void)
382 #ifdef CONFIG_FSL_IFC
383 init_early_memctl_regs(); /* tighten IFC timing */
385 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
395 #ifdef CONFIG_CHAIN_OF_TRUST
396 /* In case of Secure Boot, the IBR configures the SMMU
397 * to allow only Secure transactions.
398 * SMMU must be reset in bypass mode.
399 * Set the ClientPD bit and Clear the USFCFG Bit
401 if (fsl_check_boot_mode_secure() == 1)
405 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
406 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
407 defined(CONFIG_ARCH_LX2162A)
412 /* Get VDD in the unit mV from voltage ID */
413 int get_core_volt_from_fuse(void)
415 struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
420 /* get the voltage ID from fuse status register */
421 fusesr = in_le32(&gur->dcfg_fusesr);
422 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
423 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
424 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
425 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
426 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
427 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
429 debug("%s: VID = 0x%x\n", __func__, vid);
431 case 0x00: /* VID isn't supported */
433 debug("%s: The VID feature is not supported\n", __func__);
435 case 0x08: /* 0.9V silicon */
438 case 0x10: /* 1.0V silicon */
441 default: /* Other core voltage */
443 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
446 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
451 #elif defined(CONFIG_FSL_LSCH2)
453 * This erratum requires setting a value to eddrtqcr1 to optimal
454 * the DDR performance. The eddrtqcr1 register is in SCFG space
455 * of LS1043A and the offset is 0x157_020c.
457 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
458 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
459 #error A009660 and A008514 can not be both enabled.
462 static void erratum_a009660(void)
464 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
465 u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
466 out_be32(eddrtqcr1, 0x63b20042);
470 static void erratum_a008850_early(void)
472 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
474 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
475 CONFIG_SYS_CCI400_OFFSET);
476 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
478 /* Skip if running at lower exception level */
479 if (current_el() < 3)
482 /* disables propagation of barrier transactions to DDRC from CCI400 */
483 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
485 /* disable the re-ordering in DDRC */
486 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
490 void erratum_a008850_post(void)
492 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
494 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
495 CONFIG_SYS_CCI400_OFFSET);
496 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
499 /* Skip if running at lower exception level */
500 if (current_el() < 3)
503 /* enable propagation of barrier transactions to DDRC from CCI400 */
504 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
506 /* enable the re-ordering in DDRC */
507 tmp = ddr_in32(&ddr->eor);
508 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
509 ddr_out32(&ddr->eor, tmp);
513 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
514 void erratum_a010315(void)
518 for (i = PCIE1; i <= PCIE4; i++)
519 if (!is_serdes_configured(i)) {
520 debug("PCIe%d: disabled all R/W permission!\n", i);
521 set_pcie_ns_access(i, 0);
526 static void erratum_a010539(void)
528 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
529 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
532 porsr1 = in_be32(&gur->porsr1);
533 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
534 out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
536 out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
540 /* Get VDD in the unit mV from voltage ID */
541 int get_core_volt_from_fuse(void)
543 struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
548 fusesr = in_be32(&gur->dcfg_fusesr);
549 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
550 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
551 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
552 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
553 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
554 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
556 debug("%s: VID = 0x%x\n", __func__, vid);
558 case 0x00: /* VID isn't supported */
560 debug("%s: The VID feature is not supported\n", __func__);
562 case 0x08: /* 0.9V silicon */
565 case 0x10: /* 1.0V silicon */
568 default: /* Other core voltage */
570 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
573 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
578 static int setup_core_volt(u32 vdd)
580 return board_setup_core_volt(vdd);
583 #ifdef CONFIG_SYS_FSL_DDR
584 static void ddr_enable_0v9_volt(bool en)
586 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
589 tmp = ddr_in32(&ddr->ddr_cdr1);
592 tmp |= DDR_CDR1_V0PT9_EN;
594 tmp &= ~DDR_CDR1_V0PT9_EN;
596 ddr_out32(&ddr->ddr_cdr1, tmp);
600 int setup_chip_volt(void)
604 vdd = get_core_volt_from_fuse();
605 /* Nothing to do for silicons doesn't support VID */
609 if (setup_core_volt(vdd))
610 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
611 #ifdef CONFIG_SYS_HAS_SERDES
612 if (setup_serdes_volt(vdd))
613 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
616 #ifdef CONFIG_SYS_FSL_DDR
618 ddr_enable_0v9_volt(true);
624 #ifdef CONFIG_FSL_PFE
625 void init_pfe_scfg_dcfg_regs(void)
627 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
630 out_be32(&scfg->pfeasbcr,
631 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
632 out_be32(&scfg->pfebsbcr,
633 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
635 /* CCI-400 QoS settings for PFE */
636 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
637 | SCFG_WR_QOS1_PFE2_QOS));
638 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
639 | SCFG_RD_QOS1_PFE2_QOS));
641 ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
642 out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
643 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
647 void fsl_lsch2_early_init_f(void)
649 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
650 CONFIG_SYS_CCI400_OFFSET);
651 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
652 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
656 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
657 enable_layerscape_ns_access();
660 #ifdef CONFIG_FSL_IFC
661 init_early_memctl_regs(); /* tighten IFC timing */
664 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
665 src = get_boot_src();
666 if (src != BOOT_SOURCE_QSPI_NOR)
667 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
669 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
670 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
673 /* Make SEC reads and writes snoopable */
674 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
675 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
676 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
677 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
678 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
679 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
680 SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
681 #elif defined(CONFIG_ARCH_LS1012A)
682 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
683 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
684 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
685 SCFG_SNPCNFGCR_SATAWRSNP);
687 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
688 SCFG_SNPCNFGCR_SECWRSNP |
689 SCFG_SNPCNFGCR_SATARDSNP |
690 SCFG_SNPCNFGCR_SATAWRSNP);
694 * Enable snoop requests and DVM message requests for
695 * Slave insterface S4 (A53 core cluster)
697 if (current_el() == 3) {
698 out_le32(&cci->slave[4].snoop_ctrl,
699 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
703 * Program Central Security Unit (CSU) to grant access
704 * permission for USB 2.0 controller
706 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
707 if (current_el() == 3)
708 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
711 erratum_a008850_early(); /* part 1 of 2 */
719 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
725 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
726 int fspi_ahb_init(void)
728 /* Enable 4bytes address support and fast read */
729 u32 *fspi_lut, lut_key, *fspi_key;
731 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
732 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
734 lut_key = in_be32(fspi_key);
736 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
737 /* That means the register is BE */
738 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
739 /* Unlock the lut table */
740 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
741 /* Create READ LUT */
742 out_be32(fspi_lut, 0x0820040c);
743 out_be32(fspi_lut + 1, 0x24003008);
744 out_be32(fspi_lut + 2, 0x00000000);
745 /* Lock the lut table */
746 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
747 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
749 /* That means the register is LE */
750 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
751 /* Unlock the lut table */
752 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
753 /* Create READ LUT */
754 out_le32(fspi_lut, 0x0820040c);
755 out_le32(fspi_lut + 1, 0x24003008);
756 out_le32(fspi_lut + 2, 0x00000000);
757 /* Lock the lut table */
758 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
759 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
766 #ifdef CONFIG_QSPI_AHB_INIT
767 /* Enable 4bytes address support and fast read */
768 int qspi_ahb_init(void)
770 u32 *qspi_lut, lut_key, *qspi_key;
772 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
773 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
775 lut_key = in_be32(qspi_key);
777 if (lut_key == 0x5af05af0) {
778 /* That means the register is BE */
779 out_be32(qspi_key, 0x5af05af0);
780 /* Unlock the lut table */
781 out_be32(qspi_key + 1, 0x00000002);
782 out_be32(qspi_lut, 0x0820040c);
783 out_be32(qspi_lut + 1, 0x1c080c08);
784 out_be32(qspi_lut + 2, 0x00002400);
785 /* Lock the lut table */
786 out_be32(qspi_key, 0x5af05af0);
787 out_be32(qspi_key + 1, 0x00000001);
789 /* That means the register is LE */
790 out_le32(qspi_key, 0x5af05af0);
791 /* Unlock the lut table */
792 out_le32(qspi_key + 1, 0x00000002);
793 out_le32(qspi_lut, 0x0820040c);
794 out_le32(qspi_lut + 1, 0x1c080c08);
795 out_le32(qspi_lut + 2, 0x00002400);
796 /* Lock the lut table */
797 out_le32(qspi_key, 0x5af05af0);
798 out_le32(qspi_key + 1, 0x00000001);
805 #ifdef CONFIG_TFABOOT
806 #define MAX_BOOTCMD_SIZE 512
808 __weak int fsl_setenv_bootcmd(void)
811 enum boot_src src = get_boot_src();
812 char bootcmd_str[MAX_BOOTCMD_SIZE];
815 #ifdef IFC_NOR_BOOTCOMMAND
816 case BOOT_SOURCE_IFC_NOR:
817 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
820 #ifdef QSPI_NOR_BOOTCOMMAND
821 case BOOT_SOURCE_QSPI_NOR:
822 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
825 #ifdef XSPI_NOR_BOOTCOMMAND
826 case BOOT_SOURCE_XSPI_NOR:
827 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
830 #ifdef IFC_NAND_BOOTCOMMAND
831 case BOOT_SOURCE_IFC_NAND:
832 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
835 #ifdef QSPI_NAND_BOOTCOMMAND
836 case BOOT_SOURCE_QSPI_NAND:
837 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
840 #ifdef XSPI_NAND_BOOTCOMMAND
841 case BOOT_SOURCE_XSPI_NAND:
842 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
845 #ifdef SD_BOOTCOMMAND
846 case BOOT_SOURCE_SD_MMC:
847 sprintf(bootcmd_str, SD_BOOTCOMMAND);
850 #ifdef SD2_BOOTCOMMAND
851 case BOOT_SOURCE_SD_MMC2:
852 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
856 #ifdef QSPI_NOR_BOOTCOMMAND
857 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
862 ret = env_set("bootcmd", bootcmd_str);
864 printf("Failed to set bootcmd: ret = %d\n", ret);
870 int fsl_setenv_mcinitcmd(void)
873 enum boot_src src = get_boot_src();
876 #ifdef IFC_MC_INIT_CMD
877 case BOOT_SOURCE_IFC_NAND:
878 case BOOT_SOURCE_IFC_NOR:
879 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
882 #ifdef QSPI_MC_INIT_CMD
883 case BOOT_SOURCE_QSPI_NAND:
884 case BOOT_SOURCE_QSPI_NOR:
885 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
888 #ifdef XSPI_MC_INIT_CMD
889 case BOOT_SOURCE_XSPI_NAND:
890 case BOOT_SOURCE_XSPI_NOR:
891 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
894 #ifdef SD_MC_INIT_CMD
895 case BOOT_SOURCE_SD_MMC:
896 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
899 #ifdef SD2_MC_INIT_CMD
900 case BOOT_SOURCE_SD_MMC2:
901 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
905 #ifdef QSPI_MC_INIT_CMD
906 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
912 printf("Failed to set mcinitcmd: ret = %d\n", ret);
919 #ifdef CONFIG_BOARD_LATE_INIT
920 __weak int fsl_board_late_init(void)
925 #define DWC3_GSBUSCFG0 0xc100
926 #define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
927 #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
928 << DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
930 static void enable_dwc3_snooping(void)
932 static const char * const compatibles[] = {
933 "fsl,layerscape-dwc3",
936 fdt_addr_t dwc3_base;
941 for (i = 0; i < ARRAY_SIZE(compatibles); i++) {
942 ofnode_for_each_compatible_node(node, compatibles[i]) {
943 dwc3_base = ofnode_get_addr(node);
944 if (dwc3_base == FDT_ADDR_T_NONE)
947 val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
948 val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
949 val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
950 writel(val, dwc3_base + DWC3_GSBUSCFG0);
955 int board_late_init(void)
957 #ifdef CONFIG_CHAIN_OF_TRUST
958 fsl_setenv_chain_of_trust();
960 #ifdef CONFIG_TFABOOT
962 * Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
965 if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
966 // Set bootcmd and mcinitcmd as per boot source
967 fsl_setenv_bootcmd();
968 fsl_setenv_mcinitcmd();
969 env_set("fsl_bootcmd_mcinitcmd_set", "y");
972 #ifdef CONFIG_QSPI_AHB_INIT
975 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
979 if (IS_ENABLED(CONFIG_DM))
980 enable_dwc3_snooping();
982 return fsl_board_late_init();