1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/soc.h>
15 #include <asm/global_data.h>
16 #include <asm/arch-fsl-layerscape/config.h>
17 #include <asm/arch-fsl-layerscape/ns_access.h>
18 #include <asm/arch-fsl-layerscape/fsl_icid.h>
19 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
22 #ifdef CONFIG_SYS_FSL_DDR
23 #include <fsl_ddr_sdram.h>
26 #ifdef CONFIG_CHAIN_OF_TRUST
27 #include <fsl_validate.h>
29 #include <fsl_immap.h>
31 #include <env_internal.h>
32 DECLARE_GLOBAL_DATA_PTR;
35 bool soc_has_dp_ddr(void)
37 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
38 u32 svr = gur_in32(&gur->svr);
40 /* LS2085A, LS2088A, LS2048A has DP_DDR */
41 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
42 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
43 (SVR_SOC_VER(svr) == SVR_LS2048A))
49 bool soc_has_aiop(void)
51 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
52 u32 svr = gur_in32(&gur->svr);
54 /* LS2085A has AIOP */
55 if (SVR_SOC_VER(svr) == SVR_LS2085A)
61 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
63 scfg_clrsetbits32(scfg + offset / 4,
65 SCFG_USB_TXVREFTUNE << 6);
68 static void erratum_a009008(void)
70 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
71 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
73 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
74 defined(CONFIG_ARCH_LS1012A)
75 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
76 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
77 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
78 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
80 #elif defined(CONFIG_ARCH_LS2080A)
81 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
83 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
86 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
88 scfg_clrbits32(scfg + offset / 4,
89 SCFG_USB_SQRXTUNE_MASK << 23);
92 static void erratum_a009798(void)
94 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
95 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
97 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
98 defined(CONFIG_ARCH_LS1012A)
99 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
100 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
101 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
102 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
104 #elif defined(CONFIG_ARCH_LS2080A)
105 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
107 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
110 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
111 defined(CONFIG_ARCH_LS1012A)
112 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
114 scfg_clrsetbits32(scfg + offset / 4,
116 SCFG_USB_PCSTXSWINGFULL << 9);
120 static void erratum_a008997(void)
122 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
123 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
124 defined(CONFIG_ARCH_LS1012A)
125 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
127 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
128 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
129 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
130 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
132 #elif defined(CONFIG_ARCH_LS1028A)
133 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
135 DCSR_USB_PCSTXSWINGFULL << 11);
137 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
140 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
141 defined(CONFIG_ARCH_LS1012A)
143 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
144 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
145 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
146 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
147 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
149 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
150 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
152 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
153 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
154 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
155 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
156 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
160 static void erratum_a009007(void)
162 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
163 defined(CONFIG_ARCH_LS1012A)
164 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
166 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
167 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
168 usb_phy = (void __iomem *)SCFG_USB_PHY2;
169 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
171 usb_phy = (void __iomem *)SCFG_USB_PHY3;
172 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
174 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
175 defined(CONFIG_ARCH_LS1028A)
176 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
178 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
179 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
180 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
183 #if defined(CONFIG_FSL_LSCH3)
184 static void erratum_a050106(void)
186 #if defined(CONFIG_ARCH_LX2160A)
187 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
189 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
190 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
194 * This erratum requires setting a value to eddrtqcr1 to
195 * optimal the DDR performance.
197 static void erratum_a008336(void)
199 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
202 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
203 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
204 if (fsl_ddr_get_version(0) == 0x50200)
205 out_le32(eddrtqcr1, 0x63b30002);
207 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
208 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
209 if (fsl_ddr_get_version(0) == 0x50200)
210 out_le32(eddrtqcr1, 0x63b30002);
216 * This erratum requires a register write before being Memory
217 * controller 3 being enabled.
219 static void erratum_a008514(void)
221 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
224 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
225 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
226 out_le32(eddrtqcr1, 0x63b20002);
230 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
231 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
233 static unsigned long get_internval_val_mhz(void)
235 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
237 * interval is the number of platform cycles(MHz) between
238 * wake up events generated by EPU.
240 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
243 interval_mhz = simple_strtoul(interval, NULL, 10);
248 void erratum_a009635(void)
251 unsigned long interval_mhz = get_internval_val_mhz();
256 val = in_le32(DCSR_CGACRE5);
257 writel(val | 0x00000200, DCSR_CGACRE5);
259 val = in_le32(EPU_EPCMPR5);
260 writel(interval_mhz, EPU_EPCMPR5);
261 val = in_le32(EPU_EPCCR5);
262 writel(val | 0x82820000, EPU_EPCCR5);
263 val = in_le32(EPU_EPSMCR5);
264 writel(val | 0x002f0000, EPU_EPSMCR5);
265 val = in_le32(EPU_EPECR5);
266 writel(val | 0x20000000, EPU_EPECR5);
267 val = in_le32(EPU_EPGCR);
268 writel(val | 0x80000000, EPU_EPGCR);
270 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
272 static void erratum_rcw_src(void)
274 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
275 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
276 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
279 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
280 val &= ~DCFG_PORSR1_RCW_SRC;
281 val |= DCFG_PORSR1_RCW_SRC_NOR;
282 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
286 #define I2C_DEBUG_REG 0x6
287 #define I2C_GLITCH_EN 0x8
289 * This erratum requires setting glitch_en bit to enable
290 * digital glitch filter to improve clock stability.
292 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
293 static void erratum_a009203(void)
295 #ifdef CONFIG_SYS_I2C
297 #ifdef I2C1_BASE_ADDR
298 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
300 writeb(I2C_GLITCH_EN, ptr);
302 #ifdef I2C2_BASE_ADDR
303 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
305 writeb(I2C_GLITCH_EN, ptr);
307 #ifdef I2C3_BASE_ADDR
308 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
310 writeb(I2C_GLITCH_EN, ptr);
312 #ifdef I2C4_BASE_ADDR
313 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
315 writeb(I2C_GLITCH_EN, ptr);
321 void bypass_smmu(void)
324 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
325 out_le32(SMMU_SCR0, val);
326 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
327 out_le32(SMMU_NSCR0, val);
329 void fsl_lsch3_early_init_f(void)
332 #ifdef CONFIG_FSL_IFC
333 init_early_memctl_regs(); /* tighten IFC timing */
335 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
345 #ifdef CONFIG_CHAIN_OF_TRUST
346 /* In case of Secure Boot, the IBR configures the SMMU
347 * to allow only Secure transactions.
348 * SMMU must be reset in bypass mode.
349 * Set the ClientPD bit and Clear the USFCFG Bit
351 if (fsl_check_boot_mode_secure() == 1)
355 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
356 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
361 /* Get VDD in the unit mV from voltage ID */
362 int get_core_volt_from_fuse(void)
364 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
369 /* get the voltage ID from fuse status register */
370 fusesr = in_le32(&gur->dcfg_fusesr);
371 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
372 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
373 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
374 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
375 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
376 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
378 debug("%s: VID = 0x%x\n", __func__, vid);
380 case 0x00: /* VID isn't supported */
382 debug("%s: The VID feature is not supported\n", __func__);
384 case 0x08: /* 0.9V silicon */
387 case 0x10: /* 1.0V silicon */
390 default: /* Other core voltage */
392 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
395 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
400 #elif defined(CONFIG_FSL_LSCH2)
402 static void erratum_a009929(void)
404 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
405 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
406 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
407 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
409 rstrqmr1 |= 0x00000400;
410 gur_out32(&gur->rstrqmr1, rstrqmr1);
411 writel(0x01000000, dcsr_cop_ccp);
416 * This erratum requires setting a value to eddrtqcr1 to optimal
417 * the DDR performance. The eddrtqcr1 register is in SCFG space
418 * of LS1043A and the offset is 0x157_020c.
420 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
421 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
422 #error A009660 and A008514 can not be both enabled.
425 static void erratum_a009660(void)
427 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
428 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
429 out_be32(eddrtqcr1, 0x63b20042);
433 static void erratum_a008850_early(void)
435 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
437 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
438 CONFIG_SYS_CCI400_OFFSET);
439 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
441 /* Skip if running at lower exception level */
442 if (current_el() < 3)
445 /* disables propagation of barrier transactions to DDRC from CCI400 */
446 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
448 /* disable the re-ordering in DDRC */
449 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
453 void erratum_a008850_post(void)
455 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
457 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
458 CONFIG_SYS_CCI400_OFFSET);
459 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
462 /* Skip if running at lower exception level */
463 if (current_el() < 3)
466 /* enable propagation of barrier transactions to DDRC from CCI400 */
467 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
469 /* enable the re-ordering in DDRC */
470 tmp = ddr_in32(&ddr->eor);
471 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
472 ddr_out32(&ddr->eor, tmp);
476 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
477 void erratum_a010315(void)
481 for (i = PCIE1; i <= PCIE4; i++)
482 if (!is_serdes_configured(i)) {
483 debug("PCIe%d: disabled all R/W permission!\n", i);
484 set_pcie_ns_access(i, 0);
489 static void erratum_a010539(void)
491 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
492 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
495 porsr1 = in_be32(&gur->porsr1);
496 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
497 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
499 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
503 /* Get VDD in the unit mV from voltage ID */
504 int get_core_volt_from_fuse(void)
506 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
511 fusesr = in_be32(&gur->dcfg_fusesr);
512 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
513 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
514 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
515 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
516 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
517 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
519 debug("%s: VID = 0x%x\n", __func__, vid);
521 case 0x00: /* VID isn't supported */
523 debug("%s: The VID feature is not supported\n", __func__);
525 case 0x08: /* 0.9V silicon */
528 case 0x10: /* 1.0V silicon */
531 default: /* Other core voltage */
533 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
536 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
541 __weak int board_switch_core_volt(u32 vdd)
546 static int setup_core_volt(u32 vdd)
548 return board_setup_core_volt(vdd);
551 #ifdef CONFIG_SYS_FSL_DDR
552 static void ddr_enable_0v9_volt(bool en)
554 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
557 tmp = ddr_in32(&ddr->ddr_cdr1);
560 tmp |= DDR_CDR1_V0PT9_EN;
562 tmp &= ~DDR_CDR1_V0PT9_EN;
564 ddr_out32(&ddr->ddr_cdr1, tmp);
568 int setup_chip_volt(void)
572 vdd = get_core_volt_from_fuse();
573 /* Nothing to do for silicons doesn't support VID */
577 if (setup_core_volt(vdd))
578 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
579 #ifdef CONFIG_SYS_HAS_SERDES
580 if (setup_serdes_volt(vdd))
581 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
584 #ifdef CONFIG_SYS_FSL_DDR
586 ddr_enable_0v9_volt(true);
592 #ifdef CONFIG_FSL_PFE
593 void init_pfe_scfg_dcfg_regs(void)
595 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
598 out_be32(&scfg->pfeasbcr,
599 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
600 out_be32(&scfg->pfebsbcr,
601 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
603 /* CCI-400 QoS settings for PFE */
604 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
605 | SCFG_WR_QOS1_PFE2_QOS));
606 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
607 | SCFG_RD_QOS1_PFE2_QOS));
609 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
610 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
611 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
615 void fsl_lsch2_early_init_f(void)
617 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
618 CONFIG_SYS_CCI400_OFFSET);
619 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
620 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
624 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
625 enable_layerscape_ns_access();
628 #ifdef CONFIG_FSL_IFC
629 init_early_memctl_regs(); /* tighten IFC timing */
632 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
633 src = get_boot_src();
634 if (src != BOOT_SOURCE_QSPI_NOR)
635 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
637 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
638 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
641 /* Make SEC reads and writes snoopable */
642 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
643 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
644 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
645 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
646 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
647 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
648 SCFG_SNPCNFGCR_SATAWRSNP);
650 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
651 SCFG_SNPCNFGCR_SECWRSNP |
652 SCFG_SNPCNFGCR_SATARDSNP |
653 SCFG_SNPCNFGCR_SATAWRSNP);
657 * Enable snoop requests and DVM message requests for
658 * Slave insterface S4 (A53 core cluster)
660 if (current_el() == 3) {
661 out_le32(&cci->slave[4].snoop_ctrl,
662 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
666 * Program Central Security Unit (CSU) to grant access
667 * permission for USB 2.0 controller
669 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
670 if (current_el() == 3)
671 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
674 erratum_a008850_early(); /* part 1 of 2 */
683 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
689 #ifdef CONFIG_QSPI_AHB_INIT
690 /* Enable 4bytes address support and fast read */
691 int qspi_ahb_init(void)
693 u32 *qspi_lut, lut_key, *qspi_key;
695 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
696 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
698 lut_key = in_be32(qspi_key);
700 if (lut_key == 0x5af05af0) {
701 /* That means the register is BE */
702 out_be32(qspi_key, 0x5af05af0);
703 /* Unlock the lut table */
704 out_be32(qspi_key + 1, 0x00000002);
705 out_be32(qspi_lut, 0x0820040c);
706 out_be32(qspi_lut + 1, 0x1c080c08);
707 out_be32(qspi_lut + 2, 0x00002400);
708 /* Lock the lut table */
709 out_be32(qspi_key, 0x5af05af0);
710 out_be32(qspi_key + 1, 0x00000001);
712 /* That means the register is LE */
713 out_le32(qspi_key, 0x5af05af0);
714 /* Unlock the lut table */
715 out_le32(qspi_key + 1, 0x00000002);
716 out_le32(qspi_lut, 0x0820040c);
717 out_le32(qspi_lut + 1, 0x1c080c08);
718 out_le32(qspi_lut + 2, 0x00002400);
719 /* Lock the lut table */
720 out_le32(qspi_key, 0x5af05af0);
721 out_le32(qspi_key + 1, 0x00000001);
728 #ifdef CONFIG_TFABOOT
729 #define MAX_BOOTCMD_SIZE 512
731 int fsl_setenv_bootcmd(void)
734 enum boot_src src = get_boot_src();
735 char bootcmd_str[MAX_BOOTCMD_SIZE];
738 #ifdef IFC_NOR_BOOTCOMMAND
739 case BOOT_SOURCE_IFC_NOR:
740 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
743 #ifdef QSPI_NOR_BOOTCOMMAND
744 case BOOT_SOURCE_QSPI_NOR:
745 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
748 #ifdef XSPI_NOR_BOOTCOMMAND
749 case BOOT_SOURCE_XSPI_NOR:
750 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
753 #ifdef IFC_NAND_BOOTCOMMAND
754 case BOOT_SOURCE_IFC_NAND:
755 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
758 #ifdef QSPI_NAND_BOOTCOMMAND
759 case BOOT_SOURCE_QSPI_NAND:
760 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
763 #ifdef XSPI_NAND_BOOTCOMMAND
764 case BOOT_SOURCE_XSPI_NAND:
765 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
768 #ifdef SD_BOOTCOMMAND
769 case BOOT_SOURCE_SD_MMC:
770 sprintf(bootcmd_str, SD_BOOTCOMMAND);
773 #ifdef SD2_BOOTCOMMAND
774 case BOOT_SOURCE_SD_MMC2:
775 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
779 #ifdef QSPI_NOR_BOOTCOMMAND
780 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
785 ret = env_set("bootcmd", bootcmd_str);
787 printf("Failed to set bootcmd: ret = %d\n", ret);
793 int fsl_setenv_mcinitcmd(void)
796 enum boot_src src = get_boot_src();
799 #ifdef IFC_MC_INIT_CMD
800 case BOOT_SOURCE_IFC_NAND:
801 case BOOT_SOURCE_IFC_NOR:
802 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
805 #ifdef QSPI_MC_INIT_CMD
806 case BOOT_SOURCE_QSPI_NAND:
807 case BOOT_SOURCE_QSPI_NOR:
808 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
811 #ifdef XSPI_MC_INIT_CMD
812 case BOOT_SOURCE_XSPI_NAND:
813 case BOOT_SOURCE_XSPI_NOR:
814 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
817 #ifdef SD_MC_INIT_CMD
818 case BOOT_SOURCE_SD_MMC:
819 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
822 #ifdef SD2_MC_INIT_CMD
823 case BOOT_SOURCE_SD_MMC2:
824 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
828 #ifdef QSPI_MC_INIT_CMD
829 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
835 printf("Failed to set mcinitcmd: ret = %d\n", ret);
842 #ifdef CONFIG_BOARD_LATE_INIT
843 __weak int fsl_board_late_init(void)
848 int board_late_init(void)
850 #ifdef CONFIG_CHAIN_OF_TRUST
851 fsl_setenv_chain_of_trust();
853 #ifdef CONFIG_TFABOOT
855 * check if gd->env_addr is default_environment; then setenv bootcmd
858 #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
859 if (gd->env_addr == (ulong)&default_environment[0]) {
861 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
863 fsl_setenv_bootcmd();
864 fsl_setenv_mcinitcmd();
868 * If the boot mode is secure, default environment is not present then
869 * setenv command needs to be run by default
871 #ifdef CONFIG_CHAIN_OF_TRUST
872 if ((fsl_check_boot_mode_secure() == 1)) {
873 fsl_setenv_bootcmd();
874 fsl_setenv_mcinitcmd();
878 #ifdef CONFIG_QSPI_AHB_INIT
882 return fsl_board_late_init();