1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
13 #include <asm/global_data.h>
14 #include <asm/arch-fsl-layerscape/config.h>
15 #include <asm/arch-fsl-layerscape/ns_access.h>
16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
17 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
20 #ifdef CONFIG_SYS_FSL_DDR
21 #include <fsl_ddr_sdram.h>
24 #ifdef CONFIG_CHAIN_OF_TRUST
25 #include <fsl_validate.h>
27 #include <fsl_immap.h>
29 #include <environment.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 bool soc_has_dp_ddr(void)
35 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
36 u32 svr = gur_in32(&gur->svr);
38 /* LS2085A, LS2088A, LS2048A has DP_DDR */
39 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
40 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
41 (SVR_SOC_VER(svr) == SVR_LS2048A))
47 bool soc_has_aiop(void)
49 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
50 u32 svr = gur_in32(&gur->svr);
52 /* LS2085A has AIOP */
53 if (SVR_SOC_VER(svr) == SVR_LS2085A)
59 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
61 scfg_clrsetbits32(scfg + offset / 4,
63 SCFG_USB_TXVREFTUNE << 6);
66 static void erratum_a009008(void)
68 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
69 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
71 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
72 defined(CONFIG_ARCH_LS1012A)
73 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
74 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
75 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
76 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
78 #elif defined(CONFIG_ARCH_LS2080A)
79 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
81 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
84 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
86 scfg_clrbits32(scfg + offset / 4,
87 SCFG_USB_SQRXTUNE_MASK << 23);
90 static void erratum_a009798(void)
92 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
93 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
95 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
96 defined(CONFIG_ARCH_LS1012A)
97 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
98 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
99 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
100 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
102 #elif defined(CONFIG_ARCH_LS2080A)
103 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
105 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
108 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
109 defined(CONFIG_ARCH_LS1012A)
110 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
112 scfg_clrsetbits32(scfg + offset / 4,
114 SCFG_USB_PCSTXSWINGFULL << 9);
118 static void erratum_a008997(void)
120 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
121 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
122 defined(CONFIG_ARCH_LS1012A)
123 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
125 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
126 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
127 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
128 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
130 #elif defined(CONFIG_ARCH_LS1028A)
131 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
133 DCSR_USB_PCSTXSWINGFULL << 11);
135 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
138 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
139 defined(CONFIG_ARCH_LS1012A)
141 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
142 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
143 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
144 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
145 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
147 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
148 defined(CONFIG_ARCH_LS1028A)
150 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
151 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
152 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
153 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
154 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
158 static void erratum_a009007(void)
160 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
161 defined(CONFIG_ARCH_LS1012A)
162 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
164 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
165 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
166 usb_phy = (void __iomem *)SCFG_USB_PHY2;
167 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
169 usb_phy = (void __iomem *)SCFG_USB_PHY3;
170 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
172 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
173 defined(CONFIG_ARCH_LS1028A)
174 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
176 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
177 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
178 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
181 #if defined(CONFIG_FSL_LSCH3)
183 * This erratum requires setting a value to eddrtqcr1 to
184 * optimal the DDR performance.
186 static void erratum_a008336(void)
188 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
191 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
192 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
193 if (fsl_ddr_get_version(0) == 0x50200)
194 out_le32(eddrtqcr1, 0x63b30002);
196 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
197 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
198 if (fsl_ddr_get_version(0) == 0x50200)
199 out_le32(eddrtqcr1, 0x63b30002);
205 * This erratum requires a register write before being Memory
206 * controller 3 being enabled.
208 static void erratum_a008514(void)
210 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
213 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
214 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
215 out_le32(eddrtqcr1, 0x63b20002);
219 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
220 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
222 static unsigned long get_internval_val_mhz(void)
224 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
226 * interval is the number of platform cycles(MHz) between
227 * wake up events generated by EPU.
229 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
232 interval_mhz = simple_strtoul(interval, NULL, 10);
237 void erratum_a009635(void)
240 unsigned long interval_mhz = get_internval_val_mhz();
245 val = in_le32(DCSR_CGACRE5);
246 writel(val | 0x00000200, DCSR_CGACRE5);
248 val = in_le32(EPU_EPCMPR5);
249 writel(interval_mhz, EPU_EPCMPR5);
250 val = in_le32(EPU_EPCCR5);
251 writel(val | 0x82820000, EPU_EPCCR5);
252 val = in_le32(EPU_EPSMCR5);
253 writel(val | 0x002f0000, EPU_EPSMCR5);
254 val = in_le32(EPU_EPECR5);
255 writel(val | 0x20000000, EPU_EPECR5);
256 val = in_le32(EPU_EPGCR);
257 writel(val | 0x80000000, EPU_EPGCR);
259 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
261 static void erratum_rcw_src(void)
263 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
264 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
265 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
268 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
269 val &= ~DCFG_PORSR1_RCW_SRC;
270 val |= DCFG_PORSR1_RCW_SRC_NOR;
271 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
275 #define I2C_DEBUG_REG 0x6
276 #define I2C_GLITCH_EN 0x8
278 * This erratum requires setting glitch_en bit to enable
279 * digital glitch filter to improve clock stability.
281 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
282 static void erratum_a009203(void)
284 #ifdef CONFIG_SYS_I2C
286 #ifdef I2C1_BASE_ADDR
287 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
289 writeb(I2C_GLITCH_EN, ptr);
291 #ifdef I2C2_BASE_ADDR
292 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
294 writeb(I2C_GLITCH_EN, ptr);
296 #ifdef I2C3_BASE_ADDR
297 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
299 writeb(I2C_GLITCH_EN, ptr);
301 #ifdef I2C4_BASE_ADDR
302 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
304 writeb(I2C_GLITCH_EN, ptr);
310 void bypass_smmu(void)
313 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
314 out_le32(SMMU_SCR0, val);
315 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
316 out_le32(SMMU_NSCR0, val);
318 void fsl_lsch3_early_init_f(void)
321 #ifdef CONFIG_FSL_IFC
322 init_early_memctl_regs(); /* tighten IFC timing */
324 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
333 #ifdef CONFIG_CHAIN_OF_TRUST
334 /* In case of Secure Boot, the IBR configures the SMMU
335 * to allow only Secure transactions.
336 * SMMU must be reset in bypass mode.
337 * Set the ClientPD bit and Clear the USFCFG Bit
339 if (fsl_check_boot_mode_secure() == 1)
344 /* Get VDD in the unit mV from voltage ID */
345 int get_core_volt_from_fuse(void)
347 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
352 /* get the voltage ID from fuse status register */
353 fusesr = in_le32(&gur->dcfg_fusesr);
354 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
355 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
356 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
357 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
358 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
359 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
361 debug("%s: VID = 0x%x\n", __func__, vid);
363 case 0x00: /* VID isn't supported */
365 debug("%s: The VID feature is not supported\n", __func__);
367 case 0x08: /* 0.9V silicon */
370 case 0x10: /* 1.0V silicon */
373 default: /* Other core voltage */
375 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
378 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
383 #elif defined(CONFIG_FSL_LSCH2)
385 static void erratum_a009929(void)
387 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
388 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
389 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
390 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
392 rstrqmr1 |= 0x00000400;
393 gur_out32(&gur->rstrqmr1, rstrqmr1);
394 writel(0x01000000, dcsr_cop_ccp);
399 * This erratum requires setting a value to eddrtqcr1 to optimal
400 * the DDR performance. The eddrtqcr1 register is in SCFG space
401 * of LS1043A and the offset is 0x157_020c.
403 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
404 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
405 #error A009660 and A008514 can not be both enabled.
408 static void erratum_a009660(void)
410 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
411 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
412 out_be32(eddrtqcr1, 0x63b20042);
416 static void erratum_a008850_early(void)
418 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
420 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
421 CONFIG_SYS_CCI400_OFFSET);
422 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
424 /* Skip if running at lower exception level */
425 if (current_el() < 3)
428 /* disables propagation of barrier transactions to DDRC from CCI400 */
429 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
431 /* disable the re-ordering in DDRC */
432 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
436 void erratum_a008850_post(void)
438 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
440 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
441 CONFIG_SYS_CCI400_OFFSET);
442 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
445 /* Skip if running at lower exception level */
446 if (current_el() < 3)
449 /* enable propagation of barrier transactions to DDRC from CCI400 */
450 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
452 /* enable the re-ordering in DDRC */
453 tmp = ddr_in32(&ddr->eor);
454 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
455 ddr_out32(&ddr->eor, tmp);
459 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
460 void erratum_a010315(void)
464 for (i = PCIE1; i <= PCIE4; i++)
465 if (!is_serdes_configured(i)) {
466 debug("PCIe%d: disabled all R/W permission!\n", i);
467 set_pcie_ns_access(i, 0);
472 static void erratum_a010539(void)
474 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
475 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
478 porsr1 = in_be32(&gur->porsr1);
479 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
480 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
482 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
486 /* Get VDD in the unit mV from voltage ID */
487 int get_core_volt_from_fuse(void)
489 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
494 fusesr = in_be32(&gur->dcfg_fusesr);
495 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
496 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
497 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
498 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
499 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
500 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
502 debug("%s: VID = 0x%x\n", __func__, vid);
504 case 0x00: /* VID isn't supported */
506 debug("%s: The VID feature is not supported\n", __func__);
508 case 0x08: /* 0.9V silicon */
511 case 0x10: /* 1.0V silicon */
514 default: /* Other core voltage */
516 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
519 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
524 __weak int board_switch_core_volt(u32 vdd)
529 static int setup_core_volt(u32 vdd)
531 return board_setup_core_volt(vdd);
534 #ifdef CONFIG_SYS_FSL_DDR
535 static void ddr_enable_0v9_volt(bool en)
537 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
540 tmp = ddr_in32(&ddr->ddr_cdr1);
543 tmp |= DDR_CDR1_V0PT9_EN;
545 tmp &= ~DDR_CDR1_V0PT9_EN;
547 ddr_out32(&ddr->ddr_cdr1, tmp);
551 int setup_chip_volt(void)
555 vdd = get_core_volt_from_fuse();
556 /* Nothing to do for silicons doesn't support VID */
560 if (setup_core_volt(vdd))
561 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
562 #ifdef CONFIG_SYS_HAS_SERDES
563 if (setup_serdes_volt(vdd))
564 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
567 #ifdef CONFIG_SYS_FSL_DDR
569 ddr_enable_0v9_volt(true);
575 #ifdef CONFIG_FSL_PFE
576 void init_pfe_scfg_dcfg_regs(void)
578 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
581 out_be32(&scfg->pfeasbcr,
582 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
583 out_be32(&scfg->pfebsbcr,
584 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
586 /* CCI-400 QoS settings for PFE */
587 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
588 | SCFG_WR_QOS1_PFE2_QOS));
589 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
590 | SCFG_RD_QOS1_PFE2_QOS));
592 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
593 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
594 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
598 void fsl_lsch2_early_init_f(void)
600 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
601 CONFIG_SYS_CCI400_OFFSET);
602 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
603 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
607 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
608 enable_layerscape_ns_access();
611 #ifdef CONFIG_FSL_IFC
612 init_early_memctl_regs(); /* tighten IFC timing */
615 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
616 src = get_boot_src();
617 if (src != BOOT_SOURCE_QSPI_NOR)
618 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
620 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
621 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
624 /* Make SEC reads and writes snoopable */
625 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
626 SCFG_SNPCNFGCR_SECWRSNP |
627 SCFG_SNPCNFGCR_SATARDSNP |
628 SCFG_SNPCNFGCR_SATAWRSNP);
631 * Enable snoop requests and DVM message requests for
632 * Slave insterface S4 (A53 core cluster)
634 if (current_el() == 3) {
635 out_le32(&cci->slave[4].snoop_ctrl,
636 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
640 * Program Central Security Unit (CSU) to grant access
641 * permission for USB 2.0 controller
643 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
644 if (current_el() == 3)
645 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
648 erratum_a008850_early(); /* part 1 of 2 */
657 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
663 #ifdef CONFIG_QSPI_AHB_INIT
664 /* Enable 4bytes address support and fast read */
665 int qspi_ahb_init(void)
667 u32 *qspi_lut, lut_key, *qspi_key;
669 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
670 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
672 lut_key = in_be32(qspi_key);
674 if (lut_key == 0x5af05af0) {
675 /* That means the register is BE */
676 out_be32(qspi_key, 0x5af05af0);
677 /* Unlock the lut table */
678 out_be32(qspi_key + 1, 0x00000002);
679 out_be32(qspi_lut, 0x0820040c);
680 out_be32(qspi_lut + 1, 0x1c080c08);
681 out_be32(qspi_lut + 2, 0x00002400);
682 /* Lock the lut table */
683 out_be32(qspi_key, 0x5af05af0);
684 out_be32(qspi_key + 1, 0x00000001);
686 /* That means the register is LE */
687 out_le32(qspi_key, 0x5af05af0);
688 /* Unlock the lut table */
689 out_le32(qspi_key + 1, 0x00000002);
690 out_le32(qspi_lut, 0x0820040c);
691 out_le32(qspi_lut + 1, 0x1c080c08);
692 out_le32(qspi_lut + 2, 0x00002400);
693 /* Lock the lut table */
694 out_le32(qspi_key, 0x5af05af0);
695 out_le32(qspi_key + 1, 0x00000001);
702 #ifdef CONFIG_TFABOOT
703 #define MAX_BOOTCMD_SIZE 512
705 int fsl_setenv_bootcmd(void)
708 enum boot_src src = get_boot_src();
709 char bootcmd_str[MAX_BOOTCMD_SIZE];
712 #ifdef IFC_NOR_BOOTCOMMAND
713 case BOOT_SOURCE_IFC_NOR:
714 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
717 #ifdef QSPI_NOR_BOOTCOMMAND
718 case BOOT_SOURCE_QSPI_NOR:
719 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
722 #ifdef XSPI_NOR_BOOTCOMMAND
723 case BOOT_SOURCE_XSPI_NOR:
724 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
727 #ifdef IFC_NAND_BOOTCOMMAND
728 case BOOT_SOURCE_IFC_NAND:
729 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
732 #ifdef QSPI_NAND_BOOTCOMMAND
733 case BOOT_SOURCE_QSPI_NAND:
734 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
737 #ifdef XSPI_NAND_BOOTCOMMAND
738 case BOOT_SOURCE_XSPI_NAND:
739 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
742 #ifdef SD_BOOTCOMMAND
743 case BOOT_SOURCE_SD_MMC:
744 sprintf(bootcmd_str, SD_BOOTCOMMAND);
747 #ifdef SD2_BOOTCOMMAND
748 case BOOT_SOURCE_SD_MMC2:
749 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
753 #ifdef QSPI_NOR_BOOTCOMMAND
754 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
759 ret = env_set("bootcmd", bootcmd_str);
761 printf("Failed to set bootcmd: ret = %d\n", ret);
767 int fsl_setenv_mcinitcmd(void)
770 enum boot_src src = get_boot_src();
773 #ifdef IFC_MC_INIT_CMD
774 case BOOT_SOURCE_IFC_NAND:
775 case BOOT_SOURCE_IFC_NOR:
776 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
779 #ifdef QSPI_MC_INIT_CMD
780 case BOOT_SOURCE_QSPI_NAND:
781 case BOOT_SOURCE_QSPI_NOR:
782 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
785 #ifdef XSPI_MC_INIT_CMD
786 case BOOT_SOURCE_XSPI_NAND:
787 case BOOT_SOURCE_XSPI_NOR:
788 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
791 #ifdef SD_MC_INIT_CMD
792 case BOOT_SOURCE_SD_MMC:
793 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
796 #ifdef SD2_MC_INIT_CMD
797 case BOOT_SOURCE_SD_MMC2:
798 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
802 #ifdef QSPI_MC_INIT_CMD
803 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
809 printf("Failed to set mcinitcmd: ret = %d\n", ret);
816 #ifdef CONFIG_BOARD_LATE_INIT
817 int board_late_init(void)
819 #ifdef CONFIG_CHAIN_OF_TRUST
820 fsl_setenv_chain_of_trust();
822 #ifdef CONFIG_TFABOOT
824 * check if gd->env_addr is default_environment; then setenv bootcmd
827 #if !defined(CONFIG_ENV_ADDR) || defined(ENV_IS_EMBEDDED)
828 if (gd->env_addr == (ulong)&default_environment[0]) {
830 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
832 fsl_setenv_bootcmd();
833 fsl_setenv_mcinitcmd();
837 * If the boot mode is secure, default environment is not present then
838 * setenv command needs to be run by default
840 #ifdef CONFIG_CHAIN_OF_TRUST
841 if ((fsl_check_boot_mode_secure() == 1)) {
842 fsl_setenv_bootcmd();
843 fsl_setenv_mcinitcmd();
847 #ifdef CONFIG_QSPI_AHB_INIT