1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
8 #include <clock_legacy.h>
11 #include <fsl_immap.h>
14 #include <linux/sizes.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/soc.h>
18 #include <asm/cache.h>
20 #include <asm/global_data.h>
21 #include <asm/arch-fsl-layerscape/config.h>
22 #include <asm/arch-fsl-layerscape/ns_access.h>
23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
24 #include <asm/gic-v3.h>
25 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
28 #ifdef CONFIG_SYS_FSL_DDR
29 #include <fsl_ddr_sdram.h>
32 #ifdef CONFIG_CHAIN_OF_TRUST
33 #include <fsl_validate.h>
35 #include <fsl_immap.h>
37 #include <env_internal.h>
40 #include <linux/err.h>
41 #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
42 DECLARE_GLOBAL_DATA_PTR;
45 #ifdef CONFIG_GIC_V3_ITS
46 int ls_gic_rd_tables_init(void *blob)
50 ret = gic_lpi_tables_init();
52 debug("%s: failed to init gic-lpi-tables\n", __func__);
58 bool soc_has_dp_ddr(void)
60 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
61 u32 svr = gur_in32(&gur->svr);
63 /* LS2085A, LS2088A, LS2048A has DP_DDR */
64 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
65 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
66 (SVR_SOC_VER(svr) == SVR_LS2048A))
72 bool soc_has_aiop(void)
74 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
75 u32 svr = gur_in32(&gur->svr);
77 /* LS2085A has AIOP */
78 if (SVR_SOC_VER(svr) == SVR_LS2085A)
84 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
86 scfg_clrsetbits32(scfg + offset / 4,
88 SCFG_USB_TXVREFTUNE << 6);
91 static void erratum_a009008(void)
93 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
94 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
96 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
97 defined(CONFIG_ARCH_LS1012A)
98 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
99 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
100 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
101 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
103 #elif defined(CONFIG_ARCH_LS2080A)
104 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
106 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
109 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
111 scfg_clrbits32(scfg + offset / 4,
112 SCFG_USB_SQRXTUNE_MASK << 23);
115 static void erratum_a009798(void)
117 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
118 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
120 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
121 defined(CONFIG_ARCH_LS1012A)
122 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
123 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
124 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
125 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
127 #elif defined(CONFIG_ARCH_LS2080A)
128 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
130 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
133 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
134 defined(CONFIG_ARCH_LS1012A)
135 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
137 scfg_clrsetbits32(scfg + offset / 4,
139 SCFG_USB_PCSTXSWINGFULL << 9);
143 static void erratum_a008997(void)
145 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
146 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
147 defined(CONFIG_ARCH_LS1012A)
148 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
150 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
151 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
152 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
153 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
155 #elif defined(CONFIG_ARCH_LS1028A)
156 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
158 DCSR_USB_PCSTXSWINGFULL << 11);
160 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
163 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
164 defined(CONFIG_ARCH_LS1012A)
166 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
167 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
168 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
169 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
170 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
172 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
173 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
175 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
176 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
177 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
178 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
179 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
183 static void erratum_a009007(void)
185 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
186 defined(CONFIG_ARCH_LS1012A)
187 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
189 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
190 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
191 usb_phy = (void __iomem *)SCFG_USB_PHY2;
192 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
194 usb_phy = (void __iomem *)SCFG_USB_PHY3;
195 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
197 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
198 defined(CONFIG_ARCH_LS1028A)
199 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
201 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
202 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
203 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
206 #if defined(CONFIG_FSL_LSCH3)
207 static void erratum_a050106(void)
209 #if defined(CONFIG_ARCH_LX2160A)
210 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
212 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
213 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
217 * This erratum requires setting a value to eddrtqcr1 to
218 * optimal the DDR performance.
220 static void erratum_a008336(void)
222 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
225 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
226 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
227 if (fsl_ddr_get_version(0) == 0x50200)
228 out_le32(eddrtqcr1, 0x63b30002);
230 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
231 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
232 if (fsl_ddr_get_version(0) == 0x50200)
233 out_le32(eddrtqcr1, 0x63b30002);
239 * This erratum requires a register write before being Memory
240 * controller 3 being enabled.
242 static void erratum_a008514(void)
244 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
247 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
248 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
249 out_le32(eddrtqcr1, 0x63b20002);
253 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
254 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
256 static unsigned long get_internval_val_mhz(void)
258 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
260 * interval is the number of platform cycles(MHz) between
261 * wake up events generated by EPU.
263 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
266 interval_mhz = simple_strtoul(interval, NULL, 10);
271 void erratum_a009635(void)
274 unsigned long interval_mhz = get_internval_val_mhz();
279 val = in_le32(DCSR_CGACRE5);
280 writel(val | 0x00000200, DCSR_CGACRE5);
282 val = in_le32(EPU_EPCMPR5);
283 writel(interval_mhz, EPU_EPCMPR5);
284 val = in_le32(EPU_EPCCR5);
285 writel(val | 0x82820000, EPU_EPCCR5);
286 val = in_le32(EPU_EPSMCR5);
287 writel(val | 0x002f0000, EPU_EPSMCR5);
288 val = in_le32(EPU_EPECR5);
289 writel(val | 0x20000000, EPU_EPECR5);
290 val = in_le32(EPU_EPGCR);
291 writel(val | 0x80000000, EPU_EPGCR);
293 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
295 static void erratum_rcw_src(void)
297 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
298 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
299 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
302 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
303 val &= ~DCFG_PORSR1_RCW_SRC;
304 val |= DCFG_PORSR1_RCW_SRC_NOR;
305 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
309 #define I2C_DEBUG_REG 0x6
310 #define I2C_GLITCH_EN 0x8
312 * This erratum requires setting glitch_en bit to enable
313 * digital glitch filter to improve clock stability.
315 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
316 static void erratum_a009203(void)
318 #ifdef CONFIG_SYS_I2C
320 #ifdef I2C1_BASE_ADDR
321 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
323 writeb(I2C_GLITCH_EN, ptr);
325 #ifdef I2C2_BASE_ADDR
326 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
328 writeb(I2C_GLITCH_EN, ptr);
330 #ifdef I2C3_BASE_ADDR
331 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
333 writeb(I2C_GLITCH_EN, ptr);
335 #ifdef I2C4_BASE_ADDR
336 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
338 writeb(I2C_GLITCH_EN, ptr);
344 void bypass_smmu(void)
347 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
348 out_le32(SMMU_SCR0, val);
349 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
350 out_le32(SMMU_NSCR0, val);
352 void fsl_lsch3_early_init_f(void)
355 #ifdef CONFIG_FSL_IFC
356 init_early_memctl_regs(); /* tighten IFC timing */
358 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
368 #ifdef CONFIG_CHAIN_OF_TRUST
369 /* In case of Secure Boot, the IBR configures the SMMU
370 * to allow only Secure transactions.
371 * SMMU must be reset in bypass mode.
372 * Set the ClientPD bit and Clear the USFCFG Bit
374 if (fsl_check_boot_mode_secure() == 1)
378 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
379 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
384 /* Get VDD in the unit mV from voltage ID */
385 int get_core_volt_from_fuse(void)
387 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
392 /* get the voltage ID from fuse status register */
393 fusesr = in_le32(&gur->dcfg_fusesr);
394 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
395 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
396 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
397 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
398 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
399 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
401 debug("%s: VID = 0x%x\n", __func__, vid);
403 case 0x00: /* VID isn't supported */
405 debug("%s: The VID feature is not supported\n", __func__);
407 case 0x08: /* 0.9V silicon */
410 case 0x10: /* 1.0V silicon */
413 default: /* Other core voltage */
415 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
418 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
423 #elif defined(CONFIG_FSL_LSCH2)
425 * This erratum requires setting a value to eddrtqcr1 to optimal
426 * the DDR performance. The eddrtqcr1 register is in SCFG space
427 * of LS1043A and the offset is 0x157_020c.
429 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
430 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
431 #error A009660 and A008514 can not be both enabled.
434 static void erratum_a009660(void)
436 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
437 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
438 out_be32(eddrtqcr1, 0x63b20042);
442 static void erratum_a008850_early(void)
444 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
446 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
447 CONFIG_SYS_CCI400_OFFSET);
448 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
450 /* Skip if running at lower exception level */
451 if (current_el() < 3)
454 /* disables propagation of barrier transactions to DDRC from CCI400 */
455 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
457 /* disable the re-ordering in DDRC */
458 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
462 void erratum_a008850_post(void)
464 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
466 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
467 CONFIG_SYS_CCI400_OFFSET);
468 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
471 /* Skip if running at lower exception level */
472 if (current_el() < 3)
475 /* enable propagation of barrier transactions to DDRC from CCI400 */
476 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
478 /* enable the re-ordering in DDRC */
479 tmp = ddr_in32(&ddr->eor);
480 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
481 ddr_out32(&ddr->eor, tmp);
485 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
486 void erratum_a010315(void)
490 for (i = PCIE1; i <= PCIE4; i++)
491 if (!is_serdes_configured(i)) {
492 debug("PCIe%d: disabled all R/W permission!\n", i);
493 set_pcie_ns_access(i, 0);
498 static void erratum_a010539(void)
500 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
501 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
504 porsr1 = in_be32(&gur->porsr1);
505 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
506 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
508 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
512 /* Get VDD in the unit mV from voltage ID */
513 int get_core_volt_from_fuse(void)
515 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
520 fusesr = in_be32(&gur->dcfg_fusesr);
521 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
522 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
523 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
524 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
525 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
526 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
528 debug("%s: VID = 0x%x\n", __func__, vid);
530 case 0x00: /* VID isn't supported */
532 debug("%s: The VID feature is not supported\n", __func__);
534 case 0x08: /* 0.9V silicon */
537 case 0x10: /* 1.0V silicon */
540 default: /* Other core voltage */
542 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
545 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
550 __weak int board_switch_core_volt(u32 vdd)
555 static int setup_core_volt(u32 vdd)
557 return board_setup_core_volt(vdd);
560 #ifdef CONFIG_SYS_FSL_DDR
561 static void ddr_enable_0v9_volt(bool en)
563 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
566 tmp = ddr_in32(&ddr->ddr_cdr1);
569 tmp |= DDR_CDR1_V0PT9_EN;
571 tmp &= ~DDR_CDR1_V0PT9_EN;
573 ddr_out32(&ddr->ddr_cdr1, tmp);
577 int setup_chip_volt(void)
581 vdd = get_core_volt_from_fuse();
582 /* Nothing to do for silicons doesn't support VID */
586 if (setup_core_volt(vdd))
587 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
588 #ifdef CONFIG_SYS_HAS_SERDES
589 if (setup_serdes_volt(vdd))
590 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
593 #ifdef CONFIG_SYS_FSL_DDR
595 ddr_enable_0v9_volt(true);
601 #ifdef CONFIG_FSL_PFE
602 void init_pfe_scfg_dcfg_regs(void)
604 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
607 out_be32(&scfg->pfeasbcr,
608 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
609 out_be32(&scfg->pfebsbcr,
610 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
612 /* CCI-400 QoS settings for PFE */
613 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
614 | SCFG_WR_QOS1_PFE2_QOS));
615 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
616 | SCFG_RD_QOS1_PFE2_QOS));
618 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
619 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
620 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
624 void fsl_lsch2_early_init_f(void)
626 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
627 CONFIG_SYS_CCI400_OFFSET);
628 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
629 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
633 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
634 enable_layerscape_ns_access();
637 #ifdef CONFIG_FSL_IFC
638 init_early_memctl_regs(); /* tighten IFC timing */
641 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
642 src = get_boot_src();
643 if (src != BOOT_SOURCE_QSPI_NOR)
644 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
646 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
647 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
650 /* Make SEC reads and writes snoopable */
651 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
652 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
653 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
654 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
655 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
656 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
657 SCFG_SNPCNFGCR_SATAWRSNP);
658 #elif defined(CONFIG_ARCH_LS1012A)
659 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
660 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
661 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
662 SCFG_SNPCNFGCR_SATAWRSNP);
664 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
665 SCFG_SNPCNFGCR_SECWRSNP |
666 SCFG_SNPCNFGCR_SATARDSNP |
667 SCFG_SNPCNFGCR_SATAWRSNP);
671 * Enable snoop requests and DVM message requests for
672 * Slave insterface S4 (A53 core cluster)
674 if (current_el() == 3) {
675 out_le32(&cci->slave[4].snoop_ctrl,
676 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
680 * Program Central Security Unit (CSU) to grant access
681 * permission for USB 2.0 controller
683 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
684 if (current_el() == 3)
685 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
688 erratum_a008850_early(); /* part 1 of 2 */
696 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
702 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
703 int fspi_ahb_init(void)
705 /* Enable 4bytes address support and fast read */
706 u32 *fspi_lut, lut_key, *fspi_key;
708 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
709 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
711 lut_key = in_be32(fspi_key);
713 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
714 /* That means the register is BE */
715 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
716 /* Unlock the lut table */
717 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
718 /* Create READ LUT */
719 out_be32(fspi_lut, 0x0820040c);
720 out_be32(fspi_lut + 1, 0x24003008);
721 out_be32(fspi_lut + 2, 0x00000000);
722 /* Lock the lut table */
723 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
724 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
726 /* That means the register is LE */
727 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
728 /* Unlock the lut table */
729 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
730 /* Create READ LUT */
731 out_le32(fspi_lut, 0x0820040c);
732 out_le32(fspi_lut + 1, 0x24003008);
733 out_le32(fspi_lut + 2, 0x00000000);
734 /* Lock the lut table */
735 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
736 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
743 #ifdef CONFIG_QSPI_AHB_INIT
744 /* Enable 4bytes address support and fast read */
745 int qspi_ahb_init(void)
747 u32 *qspi_lut, lut_key, *qspi_key;
749 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
750 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
752 lut_key = in_be32(qspi_key);
754 if (lut_key == 0x5af05af0) {
755 /* That means the register is BE */
756 out_be32(qspi_key, 0x5af05af0);
757 /* Unlock the lut table */
758 out_be32(qspi_key + 1, 0x00000002);
759 out_be32(qspi_lut, 0x0820040c);
760 out_be32(qspi_lut + 1, 0x1c080c08);
761 out_be32(qspi_lut + 2, 0x00002400);
762 /* Lock the lut table */
763 out_be32(qspi_key, 0x5af05af0);
764 out_be32(qspi_key + 1, 0x00000001);
766 /* That means the register is LE */
767 out_le32(qspi_key, 0x5af05af0);
768 /* Unlock the lut table */
769 out_le32(qspi_key + 1, 0x00000002);
770 out_le32(qspi_lut, 0x0820040c);
771 out_le32(qspi_lut + 1, 0x1c080c08);
772 out_le32(qspi_lut + 2, 0x00002400);
773 /* Lock the lut table */
774 out_le32(qspi_key, 0x5af05af0);
775 out_le32(qspi_key + 1, 0x00000001);
782 #ifdef CONFIG_TFABOOT
783 #define MAX_BOOTCMD_SIZE 512
785 int fsl_setenv_bootcmd(void)
788 enum boot_src src = get_boot_src();
789 char bootcmd_str[MAX_BOOTCMD_SIZE];
792 #ifdef IFC_NOR_BOOTCOMMAND
793 case BOOT_SOURCE_IFC_NOR:
794 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
797 #ifdef QSPI_NOR_BOOTCOMMAND
798 case BOOT_SOURCE_QSPI_NOR:
799 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
802 #ifdef XSPI_NOR_BOOTCOMMAND
803 case BOOT_SOURCE_XSPI_NOR:
804 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
807 #ifdef IFC_NAND_BOOTCOMMAND
808 case BOOT_SOURCE_IFC_NAND:
809 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
812 #ifdef QSPI_NAND_BOOTCOMMAND
813 case BOOT_SOURCE_QSPI_NAND:
814 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
817 #ifdef XSPI_NAND_BOOTCOMMAND
818 case BOOT_SOURCE_XSPI_NAND:
819 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
822 #ifdef SD_BOOTCOMMAND
823 case BOOT_SOURCE_SD_MMC:
824 sprintf(bootcmd_str, SD_BOOTCOMMAND);
827 #ifdef SD2_BOOTCOMMAND
828 case BOOT_SOURCE_SD_MMC2:
829 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
833 #ifdef QSPI_NOR_BOOTCOMMAND
834 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
839 ret = env_set("bootcmd", bootcmd_str);
841 printf("Failed to set bootcmd: ret = %d\n", ret);
847 int fsl_setenv_mcinitcmd(void)
850 enum boot_src src = get_boot_src();
853 #ifdef IFC_MC_INIT_CMD
854 case BOOT_SOURCE_IFC_NAND:
855 case BOOT_SOURCE_IFC_NOR:
856 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
859 #ifdef QSPI_MC_INIT_CMD
860 case BOOT_SOURCE_QSPI_NAND:
861 case BOOT_SOURCE_QSPI_NOR:
862 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
865 #ifdef XSPI_MC_INIT_CMD
866 case BOOT_SOURCE_XSPI_NAND:
867 case BOOT_SOURCE_XSPI_NOR:
868 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
871 #ifdef SD_MC_INIT_CMD
872 case BOOT_SOURCE_SD_MMC:
873 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
876 #ifdef SD2_MC_INIT_CMD
877 case BOOT_SOURCE_SD_MMC2:
878 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
882 #ifdef QSPI_MC_INIT_CMD
883 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
889 printf("Failed to set mcinitcmd: ret = %d\n", ret);
896 #ifdef CONFIG_BOARD_LATE_INIT
897 __weak int fsl_board_late_init(void)
902 #define DWC3_GSBUSCFG0 0xc100
903 #define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
904 #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
905 << DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
907 void enable_dwc3_snooping(void)
913 fdt_addr_t dwc3_base;
915 ret = uclass_get(UCLASS_USB, &uc);
919 uclass_foreach_dev(bus, uc) {
920 if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
921 dwc3_base = devfdt_get_addr(bus);
922 if (dwc3_base == FDT_ADDR_T_NONE) {
923 dev_err(bus, "dwc3 regs missing\n");
926 val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
927 val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
928 val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
929 writel(val, dwc3_base + DWC3_GSBUSCFG0);
934 int board_late_init(void)
936 #ifdef CONFIG_CHAIN_OF_TRUST
937 fsl_setenv_chain_of_trust();
939 #ifdef CONFIG_TFABOOT
941 * check if gd->env_addr is default_environment; then setenv bootcmd
944 #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
945 if (gd->env_addr == (ulong)&default_environment[0]) {
947 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
949 fsl_setenv_bootcmd();
950 fsl_setenv_mcinitcmd();
954 * If the boot mode is secure, default environment is not present then
955 * setenv command needs to be run by default
957 #ifdef CONFIG_CHAIN_OF_TRUST
958 if ((fsl_check_boot_mode_secure() == 1)) {
959 fsl_setenv_bootcmd();
960 fsl_setenv_mcinitcmd();
964 #ifdef CONFIG_QSPI_AHB_INIT
967 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
971 if (IS_ENABLED(CONFIG_DM))
972 enable_dwc3_snooping();
974 return fsl_board_late_init();