1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
8 #include <clock_legacy.h>
11 #include <fsl_immap.h>
14 #include <linux/sizes.h>
15 #include <asm/arch/fsl_serdes.h>
16 #include <asm/arch/soc.h>
18 #include <asm/global_data.h>
19 #include <asm/arch-fsl-layerscape/config.h>
20 #include <asm/arch-fsl-layerscape/ns_access.h>
21 #include <asm/arch-fsl-layerscape/fsl_icid.h>
22 #include <asm/gic-v3.h>
23 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
26 #ifdef CONFIG_SYS_FSL_DDR
27 #include <fsl_ddr_sdram.h>
30 #ifdef CONFIG_CHAIN_OF_TRUST
31 #include <fsl_validate.h>
33 #include <fsl_immap.h>
35 #include <env_internal.h>
37 #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
38 DECLARE_GLOBAL_DATA_PTR;
41 #ifdef CONFIG_GIC_V3_ITS
42 #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
43 #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
44 #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
45 PROPTABLE_MAX_SZ, SZ_1M)
46 static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
50 struct fdt_memory gic_rd_tables;
52 gic_rd_tables.start = base;
53 gic_rd_tables.end = base + size - 1;
54 err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
57 debug("%s: failed to add reserved memory: %d\n", __func__, err);
62 int ls_gic_rd_tables_init(void *blob)
67 gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
68 ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
72 ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
74 debug("%s: failed to init gic-lpi-tables\n", __func__);
80 bool soc_has_dp_ddr(void)
82 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
83 u32 svr = gur_in32(&gur->svr);
85 /* LS2085A, LS2088A, LS2048A has DP_DDR */
86 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
87 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
88 (SVR_SOC_VER(svr) == SVR_LS2048A))
94 bool soc_has_aiop(void)
96 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
97 u32 svr = gur_in32(&gur->svr);
99 /* LS2085A has AIOP */
100 if (SVR_SOC_VER(svr) == SVR_LS2085A)
106 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
108 scfg_clrsetbits32(scfg + offset / 4,
110 SCFG_USB_TXVREFTUNE << 6);
113 static void erratum_a009008(void)
115 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
116 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
118 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
119 defined(CONFIG_ARCH_LS1012A)
120 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
121 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
122 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
123 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
125 #elif defined(CONFIG_ARCH_LS2080A)
126 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
128 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
131 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
133 scfg_clrbits32(scfg + offset / 4,
134 SCFG_USB_SQRXTUNE_MASK << 23);
137 static void erratum_a009798(void)
139 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
140 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
142 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
143 defined(CONFIG_ARCH_LS1012A)
144 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
145 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
146 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
147 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
149 #elif defined(CONFIG_ARCH_LS2080A)
150 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
152 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
155 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
156 defined(CONFIG_ARCH_LS1012A)
157 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
159 scfg_clrsetbits32(scfg + offset / 4,
161 SCFG_USB_PCSTXSWINGFULL << 9);
165 static void erratum_a008997(void)
167 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
168 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
169 defined(CONFIG_ARCH_LS1012A)
170 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
172 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
173 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
174 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
175 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
177 #elif defined(CONFIG_ARCH_LS1028A)
178 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
180 DCSR_USB_PCSTXSWINGFULL << 11);
182 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
185 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
186 defined(CONFIG_ARCH_LS1012A)
188 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
189 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
190 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
191 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
192 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
194 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
195 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
197 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
198 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
199 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
200 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
201 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
205 static void erratum_a009007(void)
207 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
208 defined(CONFIG_ARCH_LS1012A)
209 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
211 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
212 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
213 usb_phy = (void __iomem *)SCFG_USB_PHY2;
214 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
216 usb_phy = (void __iomem *)SCFG_USB_PHY3;
217 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
219 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
220 defined(CONFIG_ARCH_LS1028A)
221 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
223 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
224 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
225 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
228 #if defined(CONFIG_FSL_LSCH3)
229 static void erratum_a050106(void)
231 #if defined(CONFIG_ARCH_LX2160A)
232 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
234 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
235 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
239 * This erratum requires setting a value to eddrtqcr1 to
240 * optimal the DDR performance.
242 static void erratum_a008336(void)
244 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
247 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
248 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
249 if (fsl_ddr_get_version(0) == 0x50200)
250 out_le32(eddrtqcr1, 0x63b30002);
252 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
253 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
254 if (fsl_ddr_get_version(0) == 0x50200)
255 out_le32(eddrtqcr1, 0x63b30002);
261 * This erratum requires a register write before being Memory
262 * controller 3 being enabled.
264 static void erratum_a008514(void)
266 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
269 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
270 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
271 out_le32(eddrtqcr1, 0x63b20002);
275 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
276 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
278 static unsigned long get_internval_val_mhz(void)
280 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
282 * interval is the number of platform cycles(MHz) between
283 * wake up events generated by EPU.
285 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
288 interval_mhz = simple_strtoul(interval, NULL, 10);
293 void erratum_a009635(void)
296 unsigned long interval_mhz = get_internval_val_mhz();
301 val = in_le32(DCSR_CGACRE5);
302 writel(val | 0x00000200, DCSR_CGACRE5);
304 val = in_le32(EPU_EPCMPR5);
305 writel(interval_mhz, EPU_EPCMPR5);
306 val = in_le32(EPU_EPCCR5);
307 writel(val | 0x82820000, EPU_EPCCR5);
308 val = in_le32(EPU_EPSMCR5);
309 writel(val | 0x002f0000, EPU_EPSMCR5);
310 val = in_le32(EPU_EPECR5);
311 writel(val | 0x20000000, EPU_EPECR5);
312 val = in_le32(EPU_EPGCR);
313 writel(val | 0x80000000, EPU_EPGCR);
315 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
317 static void erratum_rcw_src(void)
319 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
320 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
321 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
324 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
325 val &= ~DCFG_PORSR1_RCW_SRC;
326 val |= DCFG_PORSR1_RCW_SRC_NOR;
327 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
331 #define I2C_DEBUG_REG 0x6
332 #define I2C_GLITCH_EN 0x8
334 * This erratum requires setting glitch_en bit to enable
335 * digital glitch filter to improve clock stability.
337 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
338 static void erratum_a009203(void)
340 #ifdef CONFIG_SYS_I2C
342 #ifdef I2C1_BASE_ADDR
343 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
345 writeb(I2C_GLITCH_EN, ptr);
347 #ifdef I2C2_BASE_ADDR
348 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
350 writeb(I2C_GLITCH_EN, ptr);
352 #ifdef I2C3_BASE_ADDR
353 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
355 writeb(I2C_GLITCH_EN, ptr);
357 #ifdef I2C4_BASE_ADDR
358 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
360 writeb(I2C_GLITCH_EN, ptr);
366 void bypass_smmu(void)
369 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
370 out_le32(SMMU_SCR0, val);
371 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
372 out_le32(SMMU_NSCR0, val);
374 void fsl_lsch3_early_init_f(void)
377 #ifdef CONFIG_FSL_IFC
378 init_early_memctl_regs(); /* tighten IFC timing */
380 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
390 #ifdef CONFIG_CHAIN_OF_TRUST
391 /* In case of Secure Boot, the IBR configures the SMMU
392 * to allow only Secure transactions.
393 * SMMU must be reset in bypass mode.
394 * Set the ClientPD bit and Clear the USFCFG Bit
396 if (fsl_check_boot_mode_secure() == 1)
400 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
401 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
406 /* Get VDD in the unit mV from voltage ID */
407 int get_core_volt_from_fuse(void)
409 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
414 /* get the voltage ID from fuse status register */
415 fusesr = in_le32(&gur->dcfg_fusesr);
416 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
417 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
418 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
419 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
420 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
421 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
423 debug("%s: VID = 0x%x\n", __func__, vid);
425 case 0x00: /* VID isn't supported */
427 debug("%s: The VID feature is not supported\n", __func__);
429 case 0x08: /* 0.9V silicon */
432 case 0x10: /* 1.0V silicon */
435 default: /* Other core voltage */
437 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
440 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
445 #elif defined(CONFIG_FSL_LSCH2)
447 static void erratum_a009929(void)
449 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
450 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
451 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
452 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
454 rstrqmr1 |= 0x00000400;
455 gur_out32(&gur->rstrqmr1, rstrqmr1);
456 writel(0x01000000, dcsr_cop_ccp);
461 * This erratum requires setting a value to eddrtqcr1 to optimal
462 * the DDR performance. The eddrtqcr1 register is in SCFG space
463 * of LS1043A and the offset is 0x157_020c.
465 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
466 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
467 #error A009660 and A008514 can not be both enabled.
470 static void erratum_a009660(void)
472 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
473 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
474 out_be32(eddrtqcr1, 0x63b20042);
478 static void erratum_a008850_early(void)
480 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
482 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
483 CONFIG_SYS_CCI400_OFFSET);
484 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
486 /* Skip if running at lower exception level */
487 if (current_el() < 3)
490 /* disables propagation of barrier transactions to DDRC from CCI400 */
491 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
493 /* disable the re-ordering in DDRC */
494 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
498 void erratum_a008850_post(void)
500 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
502 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
503 CONFIG_SYS_CCI400_OFFSET);
504 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
507 /* Skip if running at lower exception level */
508 if (current_el() < 3)
511 /* enable propagation of barrier transactions to DDRC from CCI400 */
512 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
514 /* enable the re-ordering in DDRC */
515 tmp = ddr_in32(&ddr->eor);
516 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
517 ddr_out32(&ddr->eor, tmp);
521 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
522 void erratum_a010315(void)
526 for (i = PCIE1; i <= PCIE4; i++)
527 if (!is_serdes_configured(i)) {
528 debug("PCIe%d: disabled all R/W permission!\n", i);
529 set_pcie_ns_access(i, 0);
534 static void erratum_a010539(void)
536 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
537 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
540 porsr1 = in_be32(&gur->porsr1);
541 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
542 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
544 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
548 /* Get VDD in the unit mV from voltage ID */
549 int get_core_volt_from_fuse(void)
551 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
556 fusesr = in_be32(&gur->dcfg_fusesr);
557 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
558 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
559 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
560 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
561 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
562 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
564 debug("%s: VID = 0x%x\n", __func__, vid);
566 case 0x00: /* VID isn't supported */
568 debug("%s: The VID feature is not supported\n", __func__);
570 case 0x08: /* 0.9V silicon */
573 case 0x10: /* 1.0V silicon */
576 default: /* Other core voltage */
578 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
581 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
586 __weak int board_switch_core_volt(u32 vdd)
591 static int setup_core_volt(u32 vdd)
593 return board_setup_core_volt(vdd);
596 #ifdef CONFIG_SYS_FSL_DDR
597 static void ddr_enable_0v9_volt(bool en)
599 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
602 tmp = ddr_in32(&ddr->ddr_cdr1);
605 tmp |= DDR_CDR1_V0PT9_EN;
607 tmp &= ~DDR_CDR1_V0PT9_EN;
609 ddr_out32(&ddr->ddr_cdr1, tmp);
613 int setup_chip_volt(void)
617 vdd = get_core_volt_from_fuse();
618 /* Nothing to do for silicons doesn't support VID */
622 if (setup_core_volt(vdd))
623 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
624 #ifdef CONFIG_SYS_HAS_SERDES
625 if (setup_serdes_volt(vdd))
626 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
629 #ifdef CONFIG_SYS_FSL_DDR
631 ddr_enable_0v9_volt(true);
637 #ifdef CONFIG_FSL_PFE
638 void init_pfe_scfg_dcfg_regs(void)
640 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
643 out_be32(&scfg->pfeasbcr,
644 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
645 out_be32(&scfg->pfebsbcr,
646 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
648 /* CCI-400 QoS settings for PFE */
649 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
650 | SCFG_WR_QOS1_PFE2_QOS));
651 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
652 | SCFG_RD_QOS1_PFE2_QOS));
654 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
655 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
656 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
660 void fsl_lsch2_early_init_f(void)
662 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
663 CONFIG_SYS_CCI400_OFFSET);
664 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
665 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
669 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
670 enable_layerscape_ns_access();
673 #ifdef CONFIG_FSL_IFC
674 init_early_memctl_regs(); /* tighten IFC timing */
677 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
678 src = get_boot_src();
679 if (src != BOOT_SOURCE_QSPI_NOR)
680 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
682 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
683 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
686 /* Make SEC reads and writes snoopable */
687 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
688 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
689 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
690 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
691 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
692 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
693 SCFG_SNPCNFGCR_SATAWRSNP);
694 #elif defined(CONFIG_ARCH_LS1012A)
695 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
696 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
697 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
698 SCFG_SNPCNFGCR_SATAWRSNP);
700 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
701 SCFG_SNPCNFGCR_SECWRSNP |
702 SCFG_SNPCNFGCR_SATARDSNP |
703 SCFG_SNPCNFGCR_SATAWRSNP);
707 * Enable snoop requests and DVM message requests for
708 * Slave insterface S4 (A53 core cluster)
710 if (current_el() == 3) {
711 out_le32(&cci->slave[4].snoop_ctrl,
712 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
716 * Program Central Security Unit (CSU) to grant access
717 * permission for USB 2.0 controller
719 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
720 if (current_el() == 3)
721 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
724 erratum_a008850_early(); /* part 1 of 2 */
733 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
739 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
740 int fspi_ahb_init(void)
742 /* Enable 4bytes address support and fast read */
743 u32 *fspi_lut, lut_key, *fspi_key;
745 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
746 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
748 lut_key = in_be32(fspi_key);
750 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
751 /* That means the register is BE */
752 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
753 /* Unlock the lut table */
754 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
755 /* Create READ LUT */
756 out_be32(fspi_lut, 0x0820040c);
757 out_be32(fspi_lut + 1, 0x24003008);
758 out_be32(fspi_lut + 2, 0x00000000);
759 /* Lock the lut table */
760 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
761 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
763 /* That means the register is LE */
764 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
765 /* Unlock the lut table */
766 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
767 /* Create READ LUT */
768 out_le32(fspi_lut, 0x0820040c);
769 out_le32(fspi_lut + 1, 0x24003008);
770 out_le32(fspi_lut + 2, 0x00000000);
771 /* Lock the lut table */
772 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
773 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
780 #ifdef CONFIG_QSPI_AHB_INIT
781 /* Enable 4bytes address support and fast read */
782 int qspi_ahb_init(void)
784 u32 *qspi_lut, lut_key, *qspi_key;
786 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
787 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
789 lut_key = in_be32(qspi_key);
791 if (lut_key == 0x5af05af0) {
792 /* That means the register is BE */
793 out_be32(qspi_key, 0x5af05af0);
794 /* Unlock the lut table */
795 out_be32(qspi_key + 1, 0x00000002);
796 out_be32(qspi_lut, 0x0820040c);
797 out_be32(qspi_lut + 1, 0x1c080c08);
798 out_be32(qspi_lut + 2, 0x00002400);
799 /* Lock the lut table */
800 out_be32(qspi_key, 0x5af05af0);
801 out_be32(qspi_key + 1, 0x00000001);
803 /* That means the register is LE */
804 out_le32(qspi_key, 0x5af05af0);
805 /* Unlock the lut table */
806 out_le32(qspi_key + 1, 0x00000002);
807 out_le32(qspi_lut, 0x0820040c);
808 out_le32(qspi_lut + 1, 0x1c080c08);
809 out_le32(qspi_lut + 2, 0x00002400);
810 /* Lock the lut table */
811 out_le32(qspi_key, 0x5af05af0);
812 out_le32(qspi_key + 1, 0x00000001);
819 #ifdef CONFIG_TFABOOT
820 #define MAX_BOOTCMD_SIZE 512
822 int fsl_setenv_bootcmd(void)
825 enum boot_src src = get_boot_src();
826 char bootcmd_str[MAX_BOOTCMD_SIZE];
829 #ifdef IFC_NOR_BOOTCOMMAND
830 case BOOT_SOURCE_IFC_NOR:
831 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
834 #ifdef QSPI_NOR_BOOTCOMMAND
835 case BOOT_SOURCE_QSPI_NOR:
836 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
839 #ifdef XSPI_NOR_BOOTCOMMAND
840 case BOOT_SOURCE_XSPI_NOR:
841 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
844 #ifdef IFC_NAND_BOOTCOMMAND
845 case BOOT_SOURCE_IFC_NAND:
846 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
849 #ifdef QSPI_NAND_BOOTCOMMAND
850 case BOOT_SOURCE_QSPI_NAND:
851 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
854 #ifdef XSPI_NAND_BOOTCOMMAND
855 case BOOT_SOURCE_XSPI_NAND:
856 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
859 #ifdef SD_BOOTCOMMAND
860 case BOOT_SOURCE_SD_MMC:
861 sprintf(bootcmd_str, SD_BOOTCOMMAND);
864 #ifdef SD2_BOOTCOMMAND
865 case BOOT_SOURCE_SD_MMC2:
866 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
870 #ifdef QSPI_NOR_BOOTCOMMAND
871 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
876 ret = env_set("bootcmd", bootcmd_str);
878 printf("Failed to set bootcmd: ret = %d\n", ret);
884 int fsl_setenv_mcinitcmd(void)
887 enum boot_src src = get_boot_src();
890 #ifdef IFC_MC_INIT_CMD
891 case BOOT_SOURCE_IFC_NAND:
892 case BOOT_SOURCE_IFC_NOR:
893 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
896 #ifdef QSPI_MC_INIT_CMD
897 case BOOT_SOURCE_QSPI_NAND:
898 case BOOT_SOURCE_QSPI_NOR:
899 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
902 #ifdef XSPI_MC_INIT_CMD
903 case BOOT_SOURCE_XSPI_NAND:
904 case BOOT_SOURCE_XSPI_NOR:
905 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
908 #ifdef SD_MC_INIT_CMD
909 case BOOT_SOURCE_SD_MMC:
910 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
913 #ifdef SD2_MC_INIT_CMD
914 case BOOT_SOURCE_SD_MMC2:
915 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
919 #ifdef QSPI_MC_INIT_CMD
920 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
926 printf("Failed to set mcinitcmd: ret = %d\n", ret);
933 #ifdef CONFIG_BOARD_LATE_INIT
934 __weak int fsl_board_late_init(void)
939 int board_late_init(void)
941 #ifdef CONFIG_CHAIN_OF_TRUST
942 fsl_setenv_chain_of_trust();
944 #ifdef CONFIG_TFABOOT
946 * check if gd->env_addr is default_environment; then setenv bootcmd
949 #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
950 if (gd->env_addr == (ulong)&default_environment[0]) {
952 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
954 fsl_setenv_bootcmd();
955 fsl_setenv_mcinitcmd();
959 * If the boot mode is secure, default environment is not present then
960 * setenv command needs to be run by default
962 #ifdef CONFIG_CHAIN_OF_TRUST
963 if ((fsl_check_boot_mode_secure() == 1)) {
964 fsl_setenv_bootcmd();
965 fsl_setenv_mcinitcmd();
969 #ifdef CONFIG_QSPI_AHB_INIT
972 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
976 return fsl_board_late_init();