1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
8 #include <clock_legacy.h>
10 #include <fsl_immap.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
16 #include <asm/global_data.h>
17 #include <asm/arch-fsl-layerscape/config.h>
18 #include <asm/arch-fsl-layerscape/ns_access.h>
19 #include <asm/arch-fsl-layerscape/fsl_icid.h>
20 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
23 #ifdef CONFIG_SYS_FSL_DDR
24 #include <fsl_ddr_sdram.h>
27 #ifdef CONFIG_CHAIN_OF_TRUST
28 #include <fsl_validate.h>
30 #include <fsl_immap.h>
32 #include <env_internal.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 bool soc_has_dp_ddr(void)
38 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
39 u32 svr = gur_in32(&gur->svr);
41 /* LS2085A, LS2088A, LS2048A has DP_DDR */
42 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
43 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
44 (SVR_SOC_VER(svr) == SVR_LS2048A))
50 bool soc_has_aiop(void)
52 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
53 u32 svr = gur_in32(&gur->svr);
55 /* LS2085A has AIOP */
56 if (SVR_SOC_VER(svr) == SVR_LS2085A)
62 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
64 scfg_clrsetbits32(scfg + offset / 4,
66 SCFG_USB_TXVREFTUNE << 6);
69 static void erratum_a009008(void)
71 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
72 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
74 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
75 defined(CONFIG_ARCH_LS1012A)
76 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
77 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
78 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
79 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
81 #elif defined(CONFIG_ARCH_LS2080A)
82 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
84 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
87 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
89 scfg_clrbits32(scfg + offset / 4,
90 SCFG_USB_SQRXTUNE_MASK << 23);
93 static void erratum_a009798(void)
95 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
96 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
98 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
99 defined(CONFIG_ARCH_LS1012A)
100 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
101 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
102 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
103 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
105 #elif defined(CONFIG_ARCH_LS2080A)
106 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
108 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
111 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
112 defined(CONFIG_ARCH_LS1012A)
113 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
115 scfg_clrsetbits32(scfg + offset / 4,
117 SCFG_USB_PCSTXSWINGFULL << 9);
121 static void erratum_a008997(void)
123 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
124 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
125 defined(CONFIG_ARCH_LS1012A)
126 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
128 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
129 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
130 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
131 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
133 #elif defined(CONFIG_ARCH_LS1028A)
134 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
136 DCSR_USB_PCSTXSWINGFULL << 11);
138 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
141 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
142 defined(CONFIG_ARCH_LS1012A)
144 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
145 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
146 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
147 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
148 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
150 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
151 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
153 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
154 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
155 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
156 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
157 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
161 static void erratum_a009007(void)
163 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
164 defined(CONFIG_ARCH_LS1012A)
165 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
167 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
168 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
169 usb_phy = (void __iomem *)SCFG_USB_PHY2;
170 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
172 usb_phy = (void __iomem *)SCFG_USB_PHY3;
173 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
175 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
176 defined(CONFIG_ARCH_LS1028A)
177 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
179 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
180 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
181 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
184 #if defined(CONFIG_FSL_LSCH3)
185 static void erratum_a050106(void)
187 #if defined(CONFIG_ARCH_LX2160A)
188 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
190 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
191 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
195 * This erratum requires setting a value to eddrtqcr1 to
196 * optimal the DDR performance.
198 static void erratum_a008336(void)
200 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
203 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
204 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
205 if (fsl_ddr_get_version(0) == 0x50200)
206 out_le32(eddrtqcr1, 0x63b30002);
208 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
209 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
210 if (fsl_ddr_get_version(0) == 0x50200)
211 out_le32(eddrtqcr1, 0x63b30002);
217 * This erratum requires a register write before being Memory
218 * controller 3 being enabled.
220 static void erratum_a008514(void)
222 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
225 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
226 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
227 out_le32(eddrtqcr1, 0x63b20002);
231 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
232 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
234 static unsigned long get_internval_val_mhz(void)
236 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
238 * interval is the number of platform cycles(MHz) between
239 * wake up events generated by EPU.
241 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
244 interval_mhz = simple_strtoul(interval, NULL, 10);
249 void erratum_a009635(void)
252 unsigned long interval_mhz = get_internval_val_mhz();
257 val = in_le32(DCSR_CGACRE5);
258 writel(val | 0x00000200, DCSR_CGACRE5);
260 val = in_le32(EPU_EPCMPR5);
261 writel(interval_mhz, EPU_EPCMPR5);
262 val = in_le32(EPU_EPCCR5);
263 writel(val | 0x82820000, EPU_EPCCR5);
264 val = in_le32(EPU_EPSMCR5);
265 writel(val | 0x002f0000, EPU_EPSMCR5);
266 val = in_le32(EPU_EPECR5);
267 writel(val | 0x20000000, EPU_EPECR5);
268 val = in_le32(EPU_EPGCR);
269 writel(val | 0x80000000, EPU_EPGCR);
271 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
273 static void erratum_rcw_src(void)
275 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
276 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
277 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
280 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
281 val &= ~DCFG_PORSR1_RCW_SRC;
282 val |= DCFG_PORSR1_RCW_SRC_NOR;
283 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
287 #define I2C_DEBUG_REG 0x6
288 #define I2C_GLITCH_EN 0x8
290 * This erratum requires setting glitch_en bit to enable
291 * digital glitch filter to improve clock stability.
293 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
294 static void erratum_a009203(void)
296 #ifdef CONFIG_SYS_I2C
298 #ifdef I2C1_BASE_ADDR
299 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
301 writeb(I2C_GLITCH_EN, ptr);
303 #ifdef I2C2_BASE_ADDR
304 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
306 writeb(I2C_GLITCH_EN, ptr);
308 #ifdef I2C3_BASE_ADDR
309 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
311 writeb(I2C_GLITCH_EN, ptr);
313 #ifdef I2C4_BASE_ADDR
314 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
316 writeb(I2C_GLITCH_EN, ptr);
322 void bypass_smmu(void)
325 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
326 out_le32(SMMU_SCR0, val);
327 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
328 out_le32(SMMU_NSCR0, val);
330 void fsl_lsch3_early_init_f(void)
333 #ifdef CONFIG_FSL_IFC
334 init_early_memctl_regs(); /* tighten IFC timing */
336 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
346 #ifdef CONFIG_CHAIN_OF_TRUST
347 /* In case of Secure Boot, the IBR configures the SMMU
348 * to allow only Secure transactions.
349 * SMMU must be reset in bypass mode.
350 * Set the ClientPD bit and Clear the USFCFG Bit
352 if (fsl_check_boot_mode_secure() == 1)
356 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
357 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
362 /* Get VDD in the unit mV from voltage ID */
363 int get_core_volt_from_fuse(void)
365 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
370 /* get the voltage ID from fuse status register */
371 fusesr = in_le32(&gur->dcfg_fusesr);
372 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
373 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
374 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
375 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
376 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
377 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
379 debug("%s: VID = 0x%x\n", __func__, vid);
381 case 0x00: /* VID isn't supported */
383 debug("%s: The VID feature is not supported\n", __func__);
385 case 0x08: /* 0.9V silicon */
388 case 0x10: /* 1.0V silicon */
391 default: /* Other core voltage */
393 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
396 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
401 #elif defined(CONFIG_FSL_LSCH2)
403 static void erratum_a009929(void)
405 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
406 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
407 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
408 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
410 rstrqmr1 |= 0x00000400;
411 gur_out32(&gur->rstrqmr1, rstrqmr1);
412 writel(0x01000000, dcsr_cop_ccp);
417 * This erratum requires setting a value to eddrtqcr1 to optimal
418 * the DDR performance. The eddrtqcr1 register is in SCFG space
419 * of LS1043A and the offset is 0x157_020c.
421 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
422 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
423 #error A009660 and A008514 can not be both enabled.
426 static void erratum_a009660(void)
428 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
429 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
430 out_be32(eddrtqcr1, 0x63b20042);
434 static void erratum_a008850_early(void)
436 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
438 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
439 CONFIG_SYS_CCI400_OFFSET);
440 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
442 /* Skip if running at lower exception level */
443 if (current_el() < 3)
446 /* disables propagation of barrier transactions to DDRC from CCI400 */
447 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
449 /* disable the re-ordering in DDRC */
450 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
454 void erratum_a008850_post(void)
456 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
458 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
459 CONFIG_SYS_CCI400_OFFSET);
460 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
463 /* Skip if running at lower exception level */
464 if (current_el() < 3)
467 /* enable propagation of barrier transactions to DDRC from CCI400 */
468 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
470 /* enable the re-ordering in DDRC */
471 tmp = ddr_in32(&ddr->eor);
472 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
473 ddr_out32(&ddr->eor, tmp);
477 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
478 void erratum_a010315(void)
482 for (i = PCIE1; i <= PCIE4; i++)
483 if (!is_serdes_configured(i)) {
484 debug("PCIe%d: disabled all R/W permission!\n", i);
485 set_pcie_ns_access(i, 0);
490 static void erratum_a010539(void)
492 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
493 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
496 porsr1 = in_be32(&gur->porsr1);
497 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
498 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
500 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
504 /* Get VDD in the unit mV from voltage ID */
505 int get_core_volt_from_fuse(void)
507 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
512 fusesr = in_be32(&gur->dcfg_fusesr);
513 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
514 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
515 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
516 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
517 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
518 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
520 debug("%s: VID = 0x%x\n", __func__, vid);
522 case 0x00: /* VID isn't supported */
524 debug("%s: The VID feature is not supported\n", __func__);
526 case 0x08: /* 0.9V silicon */
529 case 0x10: /* 1.0V silicon */
532 default: /* Other core voltage */
534 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
537 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
542 __weak int board_switch_core_volt(u32 vdd)
547 static int setup_core_volt(u32 vdd)
549 return board_setup_core_volt(vdd);
552 #ifdef CONFIG_SYS_FSL_DDR
553 static void ddr_enable_0v9_volt(bool en)
555 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
558 tmp = ddr_in32(&ddr->ddr_cdr1);
561 tmp |= DDR_CDR1_V0PT9_EN;
563 tmp &= ~DDR_CDR1_V0PT9_EN;
565 ddr_out32(&ddr->ddr_cdr1, tmp);
569 int setup_chip_volt(void)
573 vdd = get_core_volt_from_fuse();
574 /* Nothing to do for silicons doesn't support VID */
578 if (setup_core_volt(vdd))
579 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
580 #ifdef CONFIG_SYS_HAS_SERDES
581 if (setup_serdes_volt(vdd))
582 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
585 #ifdef CONFIG_SYS_FSL_DDR
587 ddr_enable_0v9_volt(true);
593 #ifdef CONFIG_FSL_PFE
594 void init_pfe_scfg_dcfg_regs(void)
596 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
599 out_be32(&scfg->pfeasbcr,
600 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
601 out_be32(&scfg->pfebsbcr,
602 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
604 /* CCI-400 QoS settings for PFE */
605 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
606 | SCFG_WR_QOS1_PFE2_QOS));
607 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
608 | SCFG_RD_QOS1_PFE2_QOS));
610 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
611 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
612 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
616 void fsl_lsch2_early_init_f(void)
618 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
619 CONFIG_SYS_CCI400_OFFSET);
620 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
621 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
625 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
626 enable_layerscape_ns_access();
629 #ifdef CONFIG_FSL_IFC
630 init_early_memctl_regs(); /* tighten IFC timing */
633 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
634 src = get_boot_src();
635 if (src != BOOT_SOURCE_QSPI_NOR)
636 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
638 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
639 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
642 /* Make SEC reads and writes snoopable */
643 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
644 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
645 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
646 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
647 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
648 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
649 SCFG_SNPCNFGCR_SATAWRSNP);
651 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
652 SCFG_SNPCNFGCR_SECWRSNP |
653 SCFG_SNPCNFGCR_SATARDSNP |
654 SCFG_SNPCNFGCR_SATAWRSNP);
658 * Enable snoop requests and DVM message requests for
659 * Slave insterface S4 (A53 core cluster)
661 if (current_el() == 3) {
662 out_le32(&cci->slave[4].snoop_ctrl,
663 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
667 * Program Central Security Unit (CSU) to grant access
668 * permission for USB 2.0 controller
670 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
671 if (current_el() == 3)
672 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
675 erratum_a008850_early(); /* part 1 of 2 */
684 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
690 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
691 int fspi_ahb_init(void)
693 /* Enable 4bytes address support and fast read */
694 u32 *fspi_lut, lut_key, *fspi_key;
696 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
697 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
699 lut_key = in_be32(fspi_key);
701 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
702 /* That means the register is BE */
703 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
704 /* Unlock the lut table */
705 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
706 /* Create READ LUT */
707 out_be32(fspi_lut, 0x0820040c);
708 out_be32(fspi_lut + 1, 0x24003008);
709 out_be32(fspi_lut + 2, 0x00000000);
710 /* Lock the lut table */
711 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
712 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
714 /* That means the register is LE */
715 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
716 /* Unlock the lut table */
717 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
718 /* Create READ LUT */
719 out_le32(fspi_lut, 0x0820040c);
720 out_le32(fspi_lut + 1, 0x24003008);
721 out_le32(fspi_lut + 2, 0x00000000);
722 /* Lock the lut table */
723 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
724 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
731 #ifdef CONFIG_QSPI_AHB_INIT
732 /* Enable 4bytes address support and fast read */
733 int qspi_ahb_init(void)
735 u32 *qspi_lut, lut_key, *qspi_key;
737 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
738 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
740 lut_key = in_be32(qspi_key);
742 if (lut_key == 0x5af05af0) {
743 /* That means the register is BE */
744 out_be32(qspi_key, 0x5af05af0);
745 /* Unlock the lut table */
746 out_be32(qspi_key + 1, 0x00000002);
747 out_be32(qspi_lut, 0x0820040c);
748 out_be32(qspi_lut + 1, 0x1c080c08);
749 out_be32(qspi_lut + 2, 0x00002400);
750 /* Lock the lut table */
751 out_be32(qspi_key, 0x5af05af0);
752 out_be32(qspi_key + 1, 0x00000001);
754 /* That means the register is LE */
755 out_le32(qspi_key, 0x5af05af0);
756 /* Unlock the lut table */
757 out_le32(qspi_key + 1, 0x00000002);
758 out_le32(qspi_lut, 0x0820040c);
759 out_le32(qspi_lut + 1, 0x1c080c08);
760 out_le32(qspi_lut + 2, 0x00002400);
761 /* Lock the lut table */
762 out_le32(qspi_key, 0x5af05af0);
763 out_le32(qspi_key + 1, 0x00000001);
770 #ifdef CONFIG_TFABOOT
771 #define MAX_BOOTCMD_SIZE 512
773 int fsl_setenv_bootcmd(void)
776 enum boot_src src = get_boot_src();
777 char bootcmd_str[MAX_BOOTCMD_SIZE];
780 #ifdef IFC_NOR_BOOTCOMMAND
781 case BOOT_SOURCE_IFC_NOR:
782 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
785 #ifdef QSPI_NOR_BOOTCOMMAND
786 case BOOT_SOURCE_QSPI_NOR:
787 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
790 #ifdef XSPI_NOR_BOOTCOMMAND
791 case BOOT_SOURCE_XSPI_NOR:
792 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
795 #ifdef IFC_NAND_BOOTCOMMAND
796 case BOOT_SOURCE_IFC_NAND:
797 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
800 #ifdef QSPI_NAND_BOOTCOMMAND
801 case BOOT_SOURCE_QSPI_NAND:
802 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
805 #ifdef XSPI_NAND_BOOTCOMMAND
806 case BOOT_SOURCE_XSPI_NAND:
807 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
810 #ifdef SD_BOOTCOMMAND
811 case BOOT_SOURCE_SD_MMC:
812 sprintf(bootcmd_str, SD_BOOTCOMMAND);
815 #ifdef SD2_BOOTCOMMAND
816 case BOOT_SOURCE_SD_MMC2:
817 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
821 #ifdef QSPI_NOR_BOOTCOMMAND
822 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
827 ret = env_set("bootcmd", bootcmd_str);
829 printf("Failed to set bootcmd: ret = %d\n", ret);
835 int fsl_setenv_mcinitcmd(void)
838 enum boot_src src = get_boot_src();
841 #ifdef IFC_MC_INIT_CMD
842 case BOOT_SOURCE_IFC_NAND:
843 case BOOT_SOURCE_IFC_NOR:
844 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
847 #ifdef QSPI_MC_INIT_CMD
848 case BOOT_SOURCE_QSPI_NAND:
849 case BOOT_SOURCE_QSPI_NOR:
850 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
853 #ifdef XSPI_MC_INIT_CMD
854 case BOOT_SOURCE_XSPI_NAND:
855 case BOOT_SOURCE_XSPI_NOR:
856 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
859 #ifdef SD_MC_INIT_CMD
860 case BOOT_SOURCE_SD_MMC:
861 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
864 #ifdef SD2_MC_INIT_CMD
865 case BOOT_SOURCE_SD_MMC2:
866 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
870 #ifdef QSPI_MC_INIT_CMD
871 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
877 printf("Failed to set mcinitcmd: ret = %d\n", ret);
884 #ifdef CONFIG_BOARD_LATE_INIT
885 __weak int fsl_board_late_init(void)
890 int board_late_init(void)
892 #ifdef CONFIG_CHAIN_OF_TRUST
893 fsl_setenv_chain_of_trust();
895 #ifdef CONFIG_TFABOOT
897 * check if gd->env_addr is default_environment; then setenv bootcmd
900 #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
901 if (gd->env_addr == (ulong)&default_environment[0]) {
903 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
905 fsl_setenv_bootcmd();
906 fsl_setenv_mcinitcmd();
910 * If the boot mode is secure, default environment is not present then
911 * setenv command needs to be run by default
913 #ifdef CONFIG_CHAIN_OF_TRUST
914 if ((fsl_check_boot_mode_secure() == 1)) {
915 fsl_setenv_bootcmd();
916 fsl_setenv_mcinitcmd();
920 #ifdef CONFIG_QSPI_AHB_INIT
923 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
927 return fsl_board_late_init();