1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <asm/system.h>
12 #include <asm/arch/mp.h>
13 #include <asm/arch/soc.h>
14 #include <linux/delay.h>
16 #include <asm/arch-fsl-layerscape/soc.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 void *get_spin_tbl_addr(void)
25 phys_addr_t determine_mp_bootpg(void)
27 return (phys_addr_t)&secondary_boot_code;
30 void update_os_arch_secondary_cores(uint8_t os_arch)
32 u64 *table = get_spin_tbl_addr();
35 for (i = 1; i < CONFIG_MAX_CPUS; i++) {
36 if (os_arch == IH_ARCH_DEFAULT)
37 table[i * WORDS_PER_SPIN_TABLE_ENTRY +
38 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
40 table[i * WORDS_PER_SPIN_TABLE_ENTRY +
41 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
45 #ifdef CONFIG_FSL_LSCH3
46 void wake_secondary_core_n(int cluster, int core, int cluster_cores)
48 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
49 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
52 mpidr = ((cluster << 8) | core);
54 * mpidr_el1 register value of core which needs to be released
55 * is written to scratchrw[6] register
57 gur_out32(&gur->scratchrw[6], mpidr);
58 asm volatile("dsb st" : : : "memory");
59 rst->brrl |= 1 << ((cluster * cluster_cores) + core);
60 asm volatile("dsb st" : : : "memory");
62 * scratchrw[6] register value is polled
63 * when the value becomes zero, this means that this core is up
64 * and running, next core can be released now
66 while (gur_in32(&gur->scratchrw[6]) != 0)
71 int fsl_layerscape_wake_seconday_cores(void)
73 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
74 #ifdef CONFIG_FSL_LSCH3
75 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
76 u32 svr, ver, cluster, type;
77 int j = 0, cluster_cores = 0;
78 #elif defined(CONFIG_FSL_LSCH2)
79 struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
81 u32 cores, cpu_up_mask = 1;
83 u64 *table = get_spin_tbl_addr();
85 #ifdef COUNTER_FREQUENCY_REAL
86 /* update for secondary cores */
87 __real_cntfrq = COUNTER_FREQUENCY_REAL;
88 flush_dcache_range((unsigned long)&__real_cntfrq,
89 (unsigned long)&__real_cntfrq + 8);
93 /* Clear spin table so that secondary processors
94 * observe the correct value after waking up from wfe.
96 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
97 flush_dcache_range((unsigned long)table,
98 (unsigned long)table +
99 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
101 printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
103 #ifdef CONFIG_FSL_LSCH3
104 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
105 gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
107 svr = gur_in32(&gur->svr);
108 ver = SVR_SOC_VER(svr);
109 if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
110 gur_out32(&gur->scratchrw[6], 1);
111 asm volatile("dsb st" : : : "memory");
113 asm volatile("dsb st" : : : "memory");
116 * Release the cores out of reset one-at-a-time to avoid
120 cluster = in_le32(&gur->tp_cluster[i].lower);
121 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
122 type = initiator_type(cluster, j);
124 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
129 cluster = in_le32(&gur->tp_cluster[i].lower);
130 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
131 type = initiator_type(cluster, j);
133 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
134 wake_secondary_core_n(i, j,
138 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
140 #elif defined(CONFIG_FSL_LSCH2)
141 scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
142 scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
143 asm volatile("dsb st" : : : "memory");
144 gur_out32(&gur->brrl, cores);
145 asm volatile("dsb st" : : : "memory");
147 /* Bootup online cores */
148 scfg_out32(&scfg->corebcr, cores);
150 /* This is needed as a precautionary measure.
151 * If some code before this has accidentally released the secondary
152 * cores then the pre-bootloader code will trap them in a "wfe" unless
153 * the scratchrw[6] is set. In this case we need a sev here to get these
154 * cores moving again.
159 flush_dcache_range((unsigned long)table, (unsigned long)table +
160 CONFIG_MAX_CPUS * 64);
161 for (i = 1; i < CONFIG_MAX_CPUS; i++) {
162 if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
163 SPIN_TABLE_ELEM_STATUS_IDX])
164 cpu_up_mask |= 1 << i;
166 if (hweight32(cpu_up_mask) == hweight32(cores))
171 printf("Not all cores (0x%x) are up (0x%x)\n",
175 printf("All (%d) cores are up.\n", hweight32(cores));
180 int is_core_valid(unsigned int core)
182 return !!((1 << core) & cpu_mask());
185 static int is_pos_valid(unsigned int pos)
187 return !!((1 << pos) & cpu_pos_mask());
190 int is_core_online(u64 cpu_id)
193 int pos = id_to_core(cpu_id);
194 table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
195 return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
198 int cpu_reset(u32 nr)
200 puts("Feature is not implemented.\n");
205 int cpu_disable(u32 nr)
207 puts("Feature is not implemented.\n");
212 static int core_to_pos(int nr)
214 u32 cores = cpu_pos_mask();
219 } else if (nr >= hweight32(cores)) {
220 puts("Not a valid core number.\n");
224 for (i = 1; i < 32; i++) {
225 if (is_pos_valid(i)) {
238 int cpu_status(u32 nr)
244 table = (u64 *)get_spin_tbl_addr();
245 printf("table base @ 0x%p\n", table);
247 pos = core_to_pos(nr);
250 table = (u64 *)get_spin_tbl_addr() + pos *
251 WORDS_PER_SPIN_TABLE_ENTRY;
252 printf("table @ 0x%p\n", table);
253 printf(" addr - 0x%016llx\n",
254 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
255 printf(" status - 0x%016llx\n",
256 table[SPIN_TABLE_ELEM_STATUS_IDX]);
257 printf(" lpid - 0x%016llx\n",
258 table[SPIN_TABLE_ELEM_LPID_IDX]);
264 int cpu_release(u32 nr, int argc, char *const argv[])
267 u64 *table = (u64 *)get_spin_tbl_addr();
270 pos = core_to_pos(nr);
274 table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
275 boot_addr = simple_strtoull(argv[0], NULL, 16);
276 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
277 flush_dcache_range((unsigned long)table,
278 (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
279 asm volatile("dsb st");
282 * The secondary CPUs polling the spin-table above for a non-zero
283 * value. To save power "wfe" is called. Thus call "sev" here to
284 * wake the CPUs and let them check the spin-table again (see
285 * slave_cpu loop in lowlevel.S)