arch/arm/cpu/armv8/fsl-layerscape/mp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <image.h>
   9 #include <log.h>
  10 #include <asm/cache.h>
  11 #include <asm/io.h>
  12 #include <asm/system.h>
  13 #include <asm/arch/mp.h>
  14 #include <asm/arch/soc.h>
  15 #include <linux/delay.h>
  16 #include "cpu.h"
  17 #include <asm/arch-fsl-layerscape/soc.h>
  18 #include <efi_loader.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 void *get_spin_tbl_addr(void)
  23 {
  24         /* the spin table is at the beginning */
  25         return secondary_boot_code_start;
  26 }
  27
  28 void update_os_arch_secondary_cores(uint8_t os_arch)
  29 {
  30         u64 *table = get_spin_tbl_addr();
  31         int i;
  32
  33         for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  34                 if (os_arch == IH_ARCH_DEFAULT)
  35                         table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  36                                 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  37                 else
  38                         table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  39                                 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  40         }
  41 }
  42
  43 #ifdef CONFIG_FSL_LSCH3
  44 static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  45 {
  46         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  47         struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  48         u32 mpidr = 0;
  49
  50         mpidr = ((cluster << 8) | core);
  51         /*
  52          * mpidr_el1 register value of core which needs to be released
  53          * is written to scratchrw[6] register
  54          */
  55         gur_out32(&gur->scratchrw[6], mpidr);
  56         asm volatile("dsb st" : : : "memory");
  57         rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  58         asm volatile("dsb st" : : : "memory");
  59         /*
  60          * scratchrw[6] register value is polled
  61          * when the value becomes zero, this means that this core is up
  62          * and running, next core can be released now
  63          */
  64         while (gur_in32(&gur->scratchrw[6]) != 0)
  65                 ;
  66 }
  67 #endif
  68
  69 int fsl_layerscape_wake_seconday_cores(void)
  70 {
  71         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  72 #ifdef CONFIG_FSL_LSCH3
  73         struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  74         u32 svr, ver, cluster, type;
  75         int j = 0, cluster_cores = 0;
  76 #elif defined(CONFIG_FSL_LSCH2)
  77         struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  78 #endif
  79         u32 cores, cpu_up_mask = 1;
  80         int i, timeout = 10;
  81         u64 *table;
  82 #ifdef CONFIG_EFI_LOADER
  83         u64 reloc_addr = U32_MAX;
  84         efi_status_t ret;
  85 #endif
  86
  87 #ifdef COUNTER_FREQUENCY_REAL
  88         /* update for secondary cores */
  89         __real_cntfrq = COUNTER_FREQUENCY_REAL;
  90         flush_dcache_range((unsigned long)&__real_cntfrq,
  91                            (unsigned long)&__real_cntfrq + 8);
  92 #endif
  93
  94 #ifdef CONFIG_EFI_LOADER
  95         /*
  96          * EFI will reserve 64kb for its runtime services. This will probably
  97          * overlap with our spin table code, which is why we have to relocate
  98          * it.
  99          * Keep this after the __real_cntfrq update, so we have it when we
 100          * copy the complete section here.
 101          */
 102         ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
 103                                  EFI_RESERVED_MEMORY_TYPE,
 104                                  efi_size_in_pages(secondary_boot_code_size),
 105                                  &reloc_addr);
 106         if (ret == EFI_SUCCESS) {
 107                 debug("Relocating spin table from %llx to %llx (size %lx)\n",
 108                       (u64)secondary_boot_code_start, reloc_addr,
 109                       secondary_boot_code_size);
 110                 memcpy((void *)reloc_addr, secondary_boot_code_start,
 111                        secondary_boot_code_size);
 112                 flush_dcache_range(reloc_addr,
 113                                    reloc_addr + secondary_boot_code_size);
 114
 115                 /* set new entry point for secondary cores */
 116                 secondary_boot_addr += (void *)reloc_addr -
 117                                        secondary_boot_code_start;
 118                 flush_dcache_range((unsigned long)&secondary_boot_addr,
 119                                    (unsigned long)&secondary_boot_addr + 8);
 120
 121                 /* this will be used to reserve the memory */
 122                 secondary_boot_code_start = (void *)reloc_addr;
 123         }
 124 #endif
 125
 126         cores = cpu_mask();
 127         /* Clear spin table so that secondary processors
 128          * observe the correct value after waking up from wfe.
 129          */
 130         table = get_spin_tbl_addr();
 131         memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
 132         flush_dcache_range((unsigned long)table,
 133                            (unsigned long)table +
 134                            (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
 135
 136         debug("Waking secondary cores to start from %lx\n", gd->relocaddr);
 137
 138 #ifdef CONFIG_FSL_LSCH3
 139         gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
 140         gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
 141
 142         svr = gur_in32(&gur->svr);
 143         ver = SVR_SOC_VER(svr);
 144         if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
 145                 gur_out32(&gur->scratchrw[6], 1);
 146                 asm volatile("dsb st" : : : "memory");
 147                 rst->brrl = cores;
 148                 asm volatile("dsb st" : : : "memory");
 149         } else {
 150                 /*
 151                  * Release the cores out of reset one-at-a-time to avoid
 152                  * power spikes
 153                  */
 154                 i = 0;
 155                 cluster = in_le32(&gur->tp_cluster[i].lower);
 156                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 157                         type = initiator_type(cluster, j);
 158                         if (type &&
 159                             TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 160                                 cluster_cores++;
 161                 }
 162
 163                 do {
 164                         cluster = in_le32(&gur->tp_cluster[i].lower);
 165                         for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 166                                 type = initiator_type(cluster, j);
 167                                 if (type &&
 168                                     TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 169                                         wake_secondary_core_n(i, j,
 170                                                               cluster_cores);
 171                         }
 172                 i++;
 173                 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 174         }
 175 #elif defined(CONFIG_FSL_LSCH2)
 176         scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
 177         scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
 178         asm volatile("dsb st" : : : "memory");
 179         gur_out32(&gur->brrl, cores);
 180         asm volatile("dsb st" : : : "memory");
 181
 182         /* Bootup online cores */
 183         scfg_out32(&scfg->corebcr, cores);
 184 #endif
 185         /* This is needed as a precautionary measure.
 186          * If some code before this has accidentally  released the secondary
 187          * cores then the pre-bootloader code will trap them in a "wfe" unless
 188          * the scratchrw[6] is set. In this case we need a sev here to get these
 189          * cores moving again.
 190          */
 191         asm volatile("sev");
 192
 193         while (timeout--) {
 194                 flush_dcache_range((unsigned long)table, (unsigned long)table +
 195                                    CONFIG_MAX_CPUS * 64);
 196                 for (i = 1; i < CONFIG_MAX_CPUS; i++) {
 197                         if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
 198                                         SPIN_TABLE_ELEM_STATUS_IDX])
 199                                 cpu_up_mask |= 1 << i;
 200                 }
 201                 if (hweight32(cpu_up_mask) == hweight32(cores))
 202                         break;
 203                 udelay(10);
 204         }
 205         if (timeout <= 0) {
 206                 printf("CPU:   Failed to bring up some cores (mask 0x%x)\n",
 207                        cores ^ cpu_up_mask);
 208                 return 1;
 209         }
 210         printf("CPU:   %d cores online\n", hweight32(cores));
 211
 212         return 0;
 213 }
 214
 215 int is_core_valid(unsigned int core)
 216 {
 217         return !!((1 << core) & cpu_mask());
 218 }
 219
 220 static int is_pos_valid(unsigned int pos)
 221 {
 222         return !!((1 << pos) & cpu_pos_mask());
 223 }
 224
 225 int is_core_online(u64 cpu_id)
 226 {
 227         u64 *table = get_spin_tbl_addr();
 228         int pos = id_to_core(cpu_id);
 229         table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
 230         return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
 231 }
 232
 233 int cpu_reset(u32 nr)
 234 {
 235         puts("Feature is not implemented.\n");
 236
 237         return 0;
 238 }
 239
 240 int cpu_disable(u32 nr)
 241 {
 242         puts("Feature is not implemented.\n");
 243
 244         return 0;
 245 }
 246
 247 static int core_to_pos(int nr)
 248 {
 249         u32 cores = cpu_pos_mask();
 250         int i, count = 0;
 251
 252         if (nr == 0) {
 253                 return 0;
 254         } else if (nr >= hweight32(cores)) {
 255                 puts("Not a valid core number.\n");
 256                 return -1;
 257         }
 258
 259         for (i = 1; i < 32; i++) {
 260                 if (is_pos_valid(i)) {
 261                         count++;
 262                         if (count == nr)
 263                                 break;
 264                 }
 265         }
 266
 267         if (count != nr)
 268                 return -1;
 269
 270         return i;
 271 }
 272
 273 int cpu_status(u32 nr)
 274 {
 275         u64 *table = get_spin_tbl_addr();
 276         int pos;
 277
 278         if (nr == 0) {
 279                 printf("table base @ 0x%p\n", table);
 280         } else {
 281                 pos = core_to_pos(nr);
 282                 if (pos < 0)
 283                         return -1;
 284                 table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
 285                 printf("table @ 0x%p\n", table);
 286                 printf("   addr - 0x%016llx\n",
 287                        table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
 288                 printf("   status   - 0x%016llx\n",
 289                        table[SPIN_TABLE_ELEM_STATUS_IDX]);
 290                 printf("   lpid  - 0x%016llx\n",
 291                        table[SPIN_TABLE_ELEM_LPID_IDX]);
 292         }
 293
 294         return 0;
 295 }
 296
 297 int cpu_release(u32 nr, int argc, char *const argv[])
 298 {
 299         u64 boot_addr;
 300         u64 *table = get_spin_tbl_addr();
 301         int pos;
 302
 303         pos = core_to_pos(nr);
 304         if (pos <= 0)
 305                 return -1;
 306
 307         table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
 308         boot_addr = simple_strtoull(argv[0], NULL, 16);
 309         table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
 310         flush_dcache_range((unsigned long)table,
 311                            (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
 312         asm volatile("dsb st");
 313
 314         /*
 315          * The secondary CPUs polling the spin-table above for a non-zero
 316          * value. To save power "wfe" is called. Thus call "sev" here to
 317          * wake the CPUs and let them check the spin-table again (see
 318          * slave_cpu loop in lowlevel.S)
 319          */
 320         asm volatile("sev");
 321
 322         return 0;
 323 }