arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
   9 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  10 #include <asm/arch-fsl-layerscape/fsl_portals.h>
  11
  12 struct icid_id_table icid_tbl[] = {
  13         SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
  14         SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
  15         SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
  16         SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
  17         SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
  18         SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
  19         SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
  20         SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
  21         SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
  22 #ifdef CONFIG_FSL_CAAM
  23         SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
  24         SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
  25         SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
  26         SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
  27         SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  28         SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  29         SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
  30         SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
  31         SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  32         SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  33 #endif
  34 };
  35
  36 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
  37
  38 /* integrated PCI is handled separately as it's not part of CCSR/SCFG */
  39 #ifdef CONFIG_PCIE_ECAM_GENERIC
  40
  41 #define ECAM_IERB_BASE          0x1f0800000ULL
  42 #define ECAM_IERB_OFFSET_NA     -1
  43 #define ECAM_IERB_FUNC_CNT      ARRAY_SIZE(ierb_offset)
  44 /* cache related transaction attributes for PCIe functions */
  45 #define ECAM_IERB_MSICAR                (ECAM_IERB_BASE + 0xa400)
  46 #define ECAM_IERB_MSICAR_VALUE          0x30
  47
  48 /* offset of IERB config register per PCI function */
  49 static int ierb_offset[] = {
  50         0x0800,
  51         0x1800,
  52         0x2800,
  53         0x3800,
  54         0x4800,
  55         0x5800,
  56         0x6800,
  57         ECAM_IERB_OFFSET_NA,
  58         0x0804,
  59         0x0808,
  60         0x1804,
  61         0x1808,
  62 };
  63
  64 /*
  65  * Use a custom function for LS1028A, for now this is the only SoC with IERB
  66  * and we're currently considering reorganizing IERB for future SoCs.
  67  */
  68 void set_ecam_icids(void)
  69 {
  70         int i;
  71
  72         out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
  73
  74         for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
  75                 if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
  76                         continue;
  77
  78                 out_le32(ECAM_IERB_BASE + ierb_offset[i],
  79                          FSL_ECAM_STREAM_ID_START + i);
  80         }
  81 }
  82
  83 static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
  84                                        const char *name, uint32_t idx, u32 val)
  85 {
  86         val = cpu_to_be32(val);
  87         return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
  88                                                    strlen(name),
  89                                                    idx * sizeof(val), &val,
  90                                                    sizeof(val));
  91 }
  92
  93 static int fdt_getprop_len(void *fdt, int nodeoffset, const char *name)
  94 {
  95         int len;
  96
  97         if (fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), &len))
  98                 return len;
  99
 100         return 0;
 101 }
 102
 103 void fdt_fixup_ecam(void *blob)
 104 {
 105         int off;
 106
 107         off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
 108         if (off < 0) {
 109                 debug("ECAM node not found\n");
 110                 return;
 111         }
 112
 113         if (fdt_getprop_len(blob, off, "msi-map") != 16 ||
 114             fdt_getprop_len(blob, off, "iommu-map") != 16) {
 115                 log_err("invalid msi/iommu-map propertly size in ECAM node\n");
 116                 return;
 117         }
 118
 119         fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 2,
 120                                     FSL_ECAM_STREAM_ID_START);
 121         fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 3,
 122                                     ECAM_IERB_FUNC_CNT);
 123
 124         fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 2,
 125                                     FSL_ECAM_STREAM_ID_START);
 126         fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 3,
 127                                     ECAM_IERB_FUNC_CNT);
 128 }
 129 #endif /* CONFIG_PCIE_ECAM_GENERIC */