arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015, Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP Semiconductors
   5  *
   6  * Derived from arch/power/cpu/mpc85xx/speed.c
   7  */
   8
   9 #include <common.h>
  10 #include <linux/compiler.h>
  11 #include <fsl_ifc.h>
  12 #include <asm/processor.h>
  13 #include <asm/io.h>
  14 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/soc.h>
  17 #include "cpu.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  22 #define CONFIG_SYS_FSL_NUM_CC_PLLS      6
  23 #endif
  24
  25
  26 void get_sys_info(struct sys_info *sys_info)
  27 {
  28         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  29         struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
  30                 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
  31                 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
  32         };
  33         struct ccsr_clk_ctrl __iomem *clk_ctrl =
  34                 (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
  35         unsigned int cpu;
  36         const u8 core_cplx_pll[16] = {
  37                 [0] = 0,        /* CC1 PPL / 1 */
  38                 [1] = 0,        /* CC1 PPL / 2 */
  39                 [2] = 0,        /* CC1 PPL / 4 */
  40                 [4] = 1,        /* CC2 PPL / 1 */
  41                 [5] = 1,        /* CC2 PPL / 2 */
  42                 [6] = 1,        /* CC2 PPL / 4 */
  43                 [8] = 2,        /* CC3 PPL / 1 */
  44                 [9] = 2,        /* CC3 PPL / 2 */
  45                 [10] = 2,       /* CC3 PPL / 4 */
  46                 [12] = 3,       /* CC4 PPL / 1 */
  47                 [13] = 3,       /* CC4 PPL / 2 */
  48                 [14] = 3,       /* CC4 PPL / 4 */
  49         };
  50
  51         const u8 core_cplx_pll_div[16] = {
  52                 [0] = 1,        /* CC1 PPL / 1 */
  53                 [1] = 2,        /* CC1 PPL / 2 */
  54                 [2] = 4,        /* CC1 PPL / 4 */
  55                 [4] = 1,        /* CC2 PPL / 1 */
  56                 [5] = 2,        /* CC2 PPL / 2 */
  57                 [6] = 4,        /* CC2 PPL / 4 */
  58                 [8] = 1,        /* CC3 PPL / 1 */
  59                 [9] = 2,        /* CC3 PPL / 2 */
  60                 [10] = 4,       /* CC3 PPL / 4 */
  61                 [12] = 1,       /* CC4 PPL / 1 */
  62                 [13] = 2,       /* CC4 PPL / 2 */
  63                 [14] = 4,       /* CC4 PPL / 4 */
  64         };
  65
  66         uint i, cluster;
  67 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
  68         uint rcw_tmp;
  69 #endif
  70         uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  71         uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  72         unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  73         int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
  74         u32 c_pll_sel, cplx_pll;
  75         void *offset;
  76
  77         sys_info->freq_systembus = sysclk;
  78 #ifdef CONFIG_DDR_CLK_FREQ
  79         sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  80 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  81         sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
  82 #endif
  83 #else
  84         sys_info->freq_ddrbus = sysclk;
  85 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  86         sys_info->freq_ddrbus2 = sysclk;
  87 #endif
  88 #endif
  89
  90         /* The freq_systembus is used to record frequency of platform PLL */
  91         sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
  92                         FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
  93                         FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
  94         sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  95                         FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
  96                         FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
  97 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  98         if (soc_has_dp_ddr()) {
  99                 sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
 100                         FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
 101                         FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
 102         } else {
 103                 sys_info->freq_ddrbus2 = 0;
 104         }
 105 #endif
 106
 107         for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 108                 /*
 109                  * fixme: prefer to combine the following into one line, but
 110                  * cannot pass compiling without warning about in_le32.
 111                  */
 112                 offset = (void *)((size_t)clk_grp[i/3] +
 113                          offsetof(struct ccsr_clk_cluster_group,
 114                                   pllngsr[i%3].gsr));
 115                 ratio[i] = (in_le32(offset) >> 1) & 0x3f;
 116                 freq_c_pll[i] = sysclk * ratio[i];
 117         }
 118
 119         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 120                 cluster = fsl_qoriq_core_to_cluster(cpu);
 121                 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
 122                             & 0xf;
 123                 cplx_pll = core_cplx_pll[c_pll_sel];
 124                 cplx_pll += cc_group[cluster] - 1;
 125                 sys_info->freq_processor[cpu] =
 126                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 127         }
 128
 129 #if defined(CONFIG_FSL_IFC)
 130         sys_info->freq_localbus = sys_info->freq_systembus /
 131                                                 CONFIG_SYS_FSL_IFC_CLK_DIV;
 132 #endif
 133
 134 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
 135 #define HWA_CGA_M2_CLK_SEL      0x00380000
 136 #define HWA_CGA_M2_CLK_SHIFT    19
 137         rcw_tmp = in_le32(&gur->rcwsr[5]);
 138         switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
 139         case 1:
 140                 sys_info->freq_cga_m2 = freq_c_pll[1];
 141                 break;
 142         case 2:
 143                 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
 144                 break;
 145         case 3:
 146                 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
 147                 break;
 148         case 4:
 149                 sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
 150                 break;
 151         case 6:
 152                 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
 153                 break;
 154         case 7:
 155                 sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
 156                 break;
 157         default:
 158                 printf("Error: Unknown peripheral clock select!\n");
 159                 break;
 160         }
 161 #endif
 162 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
 163         sys_info->freq_cga_m2 = sys_info->freq_systembus;
 164 #endif
 165 }
 166
 167 int get_clocks(void)
 168 {
 169         struct sys_info sys_info;
 170         get_sys_info(&sys_info);
 171         gd->cpu_clk = sys_info.freq_processor[0];
 172         gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
 173         gd->mem_clk = sys_info.freq_ddrbus;
 174 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 175         gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 176 #endif
 177 #if defined(CONFIG_FSL_ESDHC)
 178 #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
 179 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
 180         gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
 181 #endif
 182 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 183         gd->arch.sdhc_clk = sys_info.freq_cga_m2;
 184 #endif
 185 #else
 186         gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 187 #endif
 188 #endif /* defined(CONFIG_FSL_ESDHC) */
 189
 190         if (gd->cpu_clk != 0)
 191                 return 0;
 192         else
 193                 return 1;
 194 }
 195
 196 /********************************************
 197  * get_bus_freq
 198  * return platform clock in Hz
 199  *********************************************/
 200 ulong get_bus_freq(ulong dummy)
 201 {
 202         if (!gd->bus_clk)
 203                 get_clocks();
 204
 205         return gd->bus_clk;
 206 }
 207
 208 /********************************************
 209  * get_ddr_freq
 210  * return ddr bus freq in Hz
 211  *********************************************/
 212 ulong get_ddr_freq(ulong ctrl_num)
 213 {
 214         if (!gd->mem_clk)
 215                 get_clocks();
 216
 217         /*
 218          * DDR controller 0 & 1 are on memory complex 0
 219          * DDR controller 2 is on memory complext 1
 220          */
 221 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 222         if (ctrl_num >= 2)
 223                 return gd->arch.mem2_clk;
 224 #endif
 225
 226         return gd->mem_clk;
 227 }
 228
 229 int get_i2c_freq(ulong dummy)
 230 {
 231         return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
 232 }
 233
 234 int get_dspi_freq(ulong dummy)
 235 {
 236         return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
 237 }
 238
 239 int get_serial_clock(void)
 240 {
 241         return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
 242 }
 243
 244 unsigned int mxc_get_clock(enum mxc_clock clk)
 245 {
 246         switch (clk) {
 247         case MXC_I2C_CLK:
 248                 return get_i2c_freq(0);
 249         case MXC_DSPI_CLK:
 250                 return get_dspi_freq(0);
 251         default:
 252                 printf("Unsupported clock\n");
 253         }
 254         return 0;
 255 }