1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015, Freescale Semiconductor, Inc.
4 * Copyright 2019 NXP Semiconductors
6 * Derived from arch/power/cpu/mpc85xx/speed.c
10 #include <clock_legacy.h>
12 #include <linux/compiler.h>
14 #include <asm/processor.h>
16 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/soc.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
24 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
28 void get_sys_info(struct sys_info *sys_info)
30 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
31 struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
32 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
33 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
35 struct ccsr_clk_ctrl __iomem *clk_ctrl =
36 (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
38 const u8 core_cplx_pll[16] = {
39 [0] = 0, /* CC1 PPL / 1 */
40 [1] = 0, /* CC1 PPL / 2 */
41 [2] = 0, /* CC1 PPL / 4 */
42 [4] = 1, /* CC2 PPL / 1 */
43 [5] = 1, /* CC2 PPL / 2 */
44 [6] = 1, /* CC2 PPL / 4 */
45 [8] = 2, /* CC3 PPL / 1 */
46 [9] = 2, /* CC3 PPL / 2 */
47 [10] = 2, /* CC3 PPL / 4 */
48 [12] = 3, /* CC4 PPL / 1 */
49 [13] = 3, /* CC4 PPL / 2 */
50 [14] = 3, /* CC4 PPL / 4 */
53 const u8 core_cplx_pll_div[16] = {
54 [0] = 1, /* CC1 PPL / 1 */
55 [1] = 2, /* CC1 PPL / 2 */
56 [2] = 4, /* CC1 PPL / 4 */
57 [4] = 1, /* CC2 PPL / 1 */
58 [5] = 2, /* CC2 PPL / 2 */
59 [6] = 4, /* CC2 PPL / 4 */
60 [8] = 1, /* CC3 PPL / 1 */
61 [9] = 2, /* CC3 PPL / 2 */
62 [10] = 4, /* CC3 PPL / 4 */
63 [12] = 1, /* CC4 PPL / 1 */
64 [13] = 2, /* CC4 PPL / 2 */
65 [14] = 4, /* CC4 PPL / 4 */
69 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
72 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
73 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
74 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
75 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
76 u32 c_pll_sel, cplx_pll;
79 sys_info->freq_systembus = sysclk;
80 #ifdef CONFIG_DDR_CLK_FREQ
81 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
82 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
83 sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
86 sys_info->freq_ddrbus = sysclk;
87 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
88 sys_info->freq_ddrbus2 = sysclk;
92 /* The freq_systembus is used to record frequency of platform PLL */
93 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
94 FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
95 FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
96 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
97 FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
98 FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
99 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
100 if (soc_has_dp_ddr()) {
101 sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
102 FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
103 FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
105 sys_info->freq_ddrbus2 = 0;
109 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
111 * fixme: prefer to combine the following into one line, but
112 * cannot pass compiling without warning about in_le32.
114 offset = (void *)((size_t)clk_grp[i/3] +
115 offsetof(struct ccsr_clk_cluster_group,
117 ratio[i] = (in_le32(offset) >> 1) & 0x3f;
118 freq_c_pll[i] = sysclk * ratio[i];
121 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
122 cluster = fsl_qoriq_core_to_cluster(cpu);
123 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
125 cplx_pll = core_cplx_pll[c_pll_sel];
126 cplx_pll += cc_group[cluster] - 1;
127 sys_info->freq_processor[cpu] =
128 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
131 #if defined(CONFIG_FSL_IFC)
132 sys_info->freq_localbus = sys_info->freq_systembus /
133 CONFIG_SYS_FSL_IFC_CLK_DIV;
136 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
137 #define HWA_CGA_M2_CLK_SEL 0x00380000
138 #define HWA_CGA_M2_CLK_SHIFT 19
139 rcw_tmp = in_le32(&gur->rcwsr[5]);
140 switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
142 sys_info->freq_cga_m2 = freq_c_pll[1];
145 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
148 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
151 sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
154 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
157 sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
160 printf("Error: Unknown peripheral clock select!\n");
168 struct sys_info sys_info;
169 #ifdef CONFIG_FSL_ESDHC
172 get_sys_info(&sys_info);
173 gd->cpu_clk = sys_info.freq_processor[0];
174 gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
175 gd->mem_clk = sys_info.freq_ddrbus;
176 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
177 gd->arch.mem2_clk = sys_info.freq_ddrbus2;
180 #ifdef CONFIG_FSL_ESDHC
181 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
182 clock = sys_info.freq_cga_m2;
183 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
184 clock = sys_info.freq_systembus;
186 gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
187 gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
190 if (gd->cpu_clk != 0)
196 /********************************************
198 * return platform clock in Hz
199 *********************************************/
200 ulong get_bus_freq(ulong dummy)
208 /********************************************
210 * return ddr bus freq in Hz
211 *********************************************/
212 ulong get_ddr_freq(ulong ctrl_num)
218 * DDR controller 0 & 1 are on memory complex 0
219 * DDR controller 2 is on memory complext 1
221 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
223 return gd->arch.mem2_clk;
229 int get_i2c_freq(ulong dummy)
231 return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
234 int get_dspi_freq(ulong dummy)
236 return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
239 int get_serial_clock(void)
241 return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
244 unsigned int mxc_get_clock(enum mxc_clock clk)
248 return get_i2c_freq(0);
250 return get_dspi_freq(0);
252 printf("Unsupported clock\n");