1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016-2018 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <asm/arch/fsl_serdes.h>
15 #include <asm/arch/soc.h>
16 #include <fsl-mc/ldpaa_wriop.h>
18 #ifdef CONFIG_SYS_FSL_SRDS_1
19 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
21 #ifdef CONFIG_SYS_FSL_SRDS_2
22 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
24 #ifdef CONFIG_SYS_NXP_SRDS_3
25 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
28 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
29 #ifdef CONFIG_ARCH_LX2160A
30 int xfi_dpmac[XFI14 + 1];
31 int sgmii_dpmac[SGMII18 + 1];
32 int a25gaui_dpmac[_25GE10 + 1];
33 int xlaui_dpmac[_40GE2 + 1];
34 int caui2_dpmac[_50GE2 + 1];
35 int caui4_dpmac[_100GE2 + 1];
37 int xfi_dpmac[XFI8 + 1];
38 int sgmii_dpmac[SGMII16 + 1];
42 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
48 *The return value of this func is the serdes protocol used.
49 *Typically this function is called number of times depending
50 *upon the number of serdes blocks in the Silicon.
51 *Zero is used to denote that no serdes was enabled,
52 *this is the case when golden RCW was used where DPAA2 bring was
53 *intentionally removed to achieve boot to prompt
56 __weak int serdes_get_number(int serdes, int cfg)
61 int is_serdes_configured(enum srds_prtcl device)
65 #ifdef CONFIG_SYS_FSL_SRDS_1
66 if (!serdes1_prtcl_map[NONE])
69 ret |= serdes1_prtcl_map[device];
71 #ifdef CONFIG_SYS_FSL_SRDS_2
72 if (!serdes2_prtcl_map[NONE])
75 ret |= serdes2_prtcl_map[device];
77 #ifdef CONFIG_SYS_NXP_SRDS_3
78 if (!serdes3_prtcl_map[NONE])
81 ret |= serdes3_prtcl_map[device];
87 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
89 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
94 #ifdef CONFIG_SYS_FSL_SRDS_1
96 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
97 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
98 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
101 #ifdef CONFIG_SYS_FSL_SRDS_2
103 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
104 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
105 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
108 #ifdef CONFIG_SYS_NXP_SRDS_3
110 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
111 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
112 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
116 printf("invalid SerDes%d\n", sd);
120 cfg = serdes_get_number(sd, cfg);
122 /* Is serdes enabled at all? */
126 for (i = 0; i < SRDS_MAX_LANES; i++) {
127 if (serdes_get_prtcl(sd, cfg, i) == device)
134 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
135 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
137 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
141 if (serdes_prtcl_map[NONE])
144 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
146 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
147 cfg >>= sd_prctl_shift;
149 cfg = serdes_get_number(sd, cfg);
150 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
152 if (!is_serdes_prtcl_valid(sd, cfg))
153 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
155 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
156 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
157 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
158 debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
160 serdes_prtcl_map[lane_prtcl] = 1;
161 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
162 #ifdef CONFIG_ARCH_LX2160A
163 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
164 wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
167 if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
168 wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
171 if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
172 wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
175 if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
176 wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
179 if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
180 wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
183 if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
184 wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
188 switch (lane_prtcl) {
193 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
196 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
198 xfi_dpmac[lane_prtcl],
201 if (lane_prtcl >= SGMII1 &&
202 lane_prtcl <= SGMII16)
203 wriop_init_dpmac(sd, sgmii_dpmac[
213 /* Set the first element to indicate serdes has been initialized */
214 serdes_prtcl_map[NONE] = 1;
217 __weak int get_serdes_volt(void)
222 __weak int set_serdes_volt(int svdd)
227 #define LNAGCR0_RT_RSTB 0x00600000
229 #define RSTCTL_RESET_MASK 0x000000E0
231 #define RSTCTL_RSTREQ 0x80000000
232 #define RSTCTL_RST_DONE 0x40000000
233 #define RSTCTL_RSTERR 0x20000000
235 #define RSTCTL_SDEN 0x00000020
236 #define RSTCTL_SDRST_B 0x00000040
237 #define RSTCTL_PLLRST_B 0x00000080
239 #define TCALCR_CALRST_B 0x08000000
241 struct serdes_prctl_info {
247 struct serdes_prctl_info srds_prctl_info[] = {
248 #ifdef CONFIG_SYS_FSL_SRDS_1
250 .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
251 .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
255 #ifdef CONFIG_SYS_FSL_SRDS_2
257 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
258 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
261 #ifdef CONFIG_SYS_NXP_SRDS_3
263 .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
264 .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
270 static int get_serdes_prctl_info_idx(u32 serdes_id)
273 struct serdes_prctl_info *srds_info;
275 /* loop until NULL ENTRY defined by .id=0 */
276 for (srds_info = srds_prctl_info; srds_info->id != 0;
277 srds_info++, pos++) {
278 if (srds_info->id == serdes_id)
285 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
286 struct ccsr_serdes __iomem *serdes_base,
292 pos = get_serdes_prctl_info_idx(serdes_id);
294 printf("invalid serdes_id %d\n", serdes_id);
298 cfg_tmp = cfg & srds_prctl_info[pos].mask;
299 cfg_tmp >>= srds_prctl_info[pos].shift;
301 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
303 setbits_le32(&serdes_base->lane[i].gcr0,
306 clrbits_le32(&serdes_base->lane[i].gcr0,
311 static void do_pll_reset(u32 cfg,
312 struct ccsr_serdes __iomem *serdes_base)
316 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
317 clrbits_le32(&serdes_base->bank[i].rstctl,
321 setbits_le32(&serdes_base->bank[i].rstctl,
327 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
329 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
330 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
333 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
334 struct ccsr_serdes __iomem *serdes_base)
336 if (!(cfg == 0x3 && i == 1)) {
338 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
339 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
344 static void do_pll_reset_done(u32 cfg,
345 struct ccsr_serdes __iomem *serdes_base)
350 for (i = 0; i < 2; i++) {
351 reg = in_le32(&serdes_base->bank[i].pllcr0);
352 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
353 setbits_le32(&serdes_base->bank[i].rstctl,
359 static void do_serdes_enable(u32 cfg,
360 struct ccsr_serdes __iomem *serdes_base)
364 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
365 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
368 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
370 /* Take the Rx/Tx calibration out of reset */
371 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
375 static void do_pll_lock(u32 cfg,
376 struct ccsr_serdes __iomem *serdes_base)
381 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
382 /* if the PLL is not locked, set RST_ERR */
383 reg = in_le32(&serdes_base->bank[i].pllcr0);
384 if (!((reg >> 23) & 0x1)) {
385 setbits_le32(&serdes_base->bank[i].rstctl,
389 setbits_le32(&serdes_base->bank[i].rstctl,
396 int setup_serdes_volt(u32 svdd)
398 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
399 struct ccsr_serdes __iomem *serdes1_base =
400 (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
401 u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
402 #ifdef CONFIG_SYS_FSL_SRDS_2
403 struct ccsr_serdes __iomem *serdes2_base =
404 (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
405 u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
407 #ifdef CONFIG_SYS_NXP_SRDS_3
408 struct ccsr_serdes __iomem *serdes3_base =
409 (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
410 u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
413 int svdd_cur, svdd_tar;
416 /* Only support switch SVDD to 900mV */
420 /* Scale up to the LTC resolution is 1/4096V */
421 svdd = (svdd * 4096) / 1000;
424 svdd_cur = get_serdes_volt();
428 debug("%s: current SVDD: %x; target SVDD: %x\n",
429 __func__, svdd_cur, svdd_tar);
430 if (svdd_cur == svdd_tar)
433 /* Put the all enabled lanes in reset */
434 #ifdef CONFIG_SYS_FSL_SRDS_1
435 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
438 #ifdef CONFIG_SYS_FSL_SRDS_2
439 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
441 #ifdef CONFIG_SYS_NXP_SRDS_3
442 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
445 /* Put the all enabled PLL in reset */
446 #ifdef CONFIG_SYS_FSL_SRDS_1
447 cfg_tmp = cfg_rcwsrds1 & 0x3;
448 do_pll_reset(cfg_tmp, serdes1_base);
451 #ifdef CONFIG_SYS_FSL_SRDS_2
452 cfg_tmp = cfg_rcwsrds1 & 0xC;
454 do_pll_reset(cfg_tmp, serdes2_base);
457 #ifdef CONFIG_SYS_NXP_SRDS_3
458 cfg_tmp = cfg_rcwsrds3 & 0x30;
460 do_pll_reset(cfg_tmp, serdes3_base);
463 /* Put the Rx/Tx calibration into reset */
464 #ifdef CONFIG_SYS_FSL_SRDS_1
465 do_rx_tx_cal_reset(serdes1_base);
468 #ifdef CONFIG_SYS_FSL_SRDS_2
469 do_rx_tx_cal_reset(serdes2_base);
472 #ifdef CONFIG_SYS_NXP_SRDS_3
473 do_rx_tx_cal_reset(serdes3_base);
476 ret = set_serdes_volt(svdd);
478 printf("could not change SVDD\n");
482 /* For each PLL that’s not disabled via RCW enable the SERDES */
483 #ifdef CONFIG_SYS_FSL_SRDS_1
484 cfg_tmp = cfg_rcwsrds1 & 0x3;
485 do_serdes_enable(cfg_tmp, serdes1_base);
487 #ifdef CONFIG_SYS_FSL_SRDS_2
488 cfg_tmp = cfg_rcwsrds1 & 0xC;
490 do_serdes_enable(cfg_tmp, serdes2_base);
492 #ifdef CONFIG_SYS_NXP_SRDS_3
493 cfg_tmp = cfg_rcwsrds3 & 0x30;
495 do_serdes_enable(cfg_tmp, serdes3_base);
498 /* Wait for at at least 625us, ensure the PLLs being reset are locked */
501 #ifdef CONFIG_SYS_FSL_SRDS_1
502 cfg_tmp = cfg_rcwsrds1 & 0x3;
503 do_pll_lock(cfg_tmp, serdes1_base);
506 #ifdef CONFIG_SYS_FSL_SRDS_2
507 cfg_tmp = cfg_rcwsrds1 & 0xC;
509 do_pll_lock(cfg_tmp, serdes2_base);
512 #ifdef CONFIG_SYS_NXP_SRDS_3
513 cfg_tmp = cfg_rcwsrds3 & 0x30;
515 do_pll_lock(cfg_tmp, serdes3_base);
518 /* Take the all enabled lanes out of reset */
519 #ifdef CONFIG_SYS_FSL_SRDS_1
520 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
522 #ifdef CONFIG_SYS_FSL_SRDS_2
523 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
526 #ifdef CONFIG_SYS_NXP_SRDS_3
527 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
530 /* For each PLL being reset, and achieved PLL lock set RST_DONE */
531 #ifdef CONFIG_SYS_FSL_SRDS_1
532 cfg_tmp = cfg_rcwsrds1 & 0x3;
533 do_pll_reset_done(cfg_tmp, serdes1_base);
535 #ifdef CONFIG_SYS_FSL_SRDS_2
536 cfg_tmp = cfg_rcwsrds1 & 0xC;
538 do_pll_reset_done(cfg_tmp, serdes2_base);
541 #ifdef CONFIG_SYS_NXP_SRDS_3
542 cfg_tmp = cfg_rcwsrds3 & 0x30;
544 do_pll_reset_done(cfg_tmp, serdes3_base);
550 void fsl_serdes_init(void)
552 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
555 #ifdef CONFIG_ARCH_LX2160A
556 for (i = XFI1, j = 1; i <= XFI14; i++, j++)
559 for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
562 for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
563 a25gaui_dpmac[i] = j;
565 for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
568 for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
571 for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
574 for (i = XFI1, j = 1; i <= XFI8; i++, j++)
577 for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
582 #ifdef CONFIG_SYS_FSL_SRDS_1
583 serdes_init(FSL_SRDS_1,
584 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
585 FSL_CHASSIS3_SRDS1_REGSR,
586 FSL_CHASSIS3_SRDS1_PRTCL_MASK,
587 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
590 #ifdef CONFIG_SYS_FSL_SRDS_2
591 serdes_init(FSL_SRDS_2,
592 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
593 FSL_CHASSIS3_SRDS2_REGSR,
594 FSL_CHASSIS3_SRDS2_PRTCL_MASK,
595 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
598 #ifdef CONFIG_SYS_NXP_SRDS_3
599 serdes_init(NXP_SRDS_3,
600 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
601 FSL_CHASSIS3_SRDS3_REGSR,
602 FSL_CHASSIS3_SRDS3_PRTCL_MASK,
603 FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
608 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
610 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
611 char scfg[16], snum[16];
615 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
616 cfg >>= sd_prctl_shift;
617 cfg = serdes_get_number(sd, cfg);
619 #if defined(SRDS_BITS_PER_LANE)
621 * reverse lanes, lane 0 should be printed first so it must be moved to
623 * For example bb58 should read 85bb, lane 0 being protocol 8.
624 * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
625 * independent per-lane protocol configuration, at this time LS1028A and
626 * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
627 * lanes as a single value.
629 for (int i = 0; i < SRDS_MAX_LANES; i++) {
632 tmp = cfg >> (i * SRDS_BITS_PER_LANE);
633 tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
634 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
637 #endif /* SRDS_BITS_PER_LANE */
639 snprintf(snum, 16, "serdes%d", sd);
640 snprintf(scfg, 16, "%x", cfgr);
646 int serdes_misc_init(void)
648 #ifdef CONFIG_SYS_FSL_SRDS_1
649 serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
650 FSL_CHASSIS3_SRDS1_PRTCL_MASK,
651 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
653 #ifdef CONFIG_SYS_FSL_SRDS_2
654 serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
655 FSL_CHASSIS3_SRDS2_PRTCL_MASK,
656 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
658 #ifdef CONFIG_SYS_NXP_SRDS_3
659 serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
660 FSL_CHASSIS3_SRDS3_PRTCL_MASK,
661 FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);