1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016-2018, 2020 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <asm/arch/fsl_serdes.h>
15 #include <asm/arch/soc.h>
16 #include <fsl-mc/ldpaa_wriop.h>
18 #ifdef CONFIG_SYS_FSL_SRDS_1
19 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
21 #ifdef CONFIG_SYS_FSL_SRDS_2
22 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
24 #ifdef CONFIG_SYS_NXP_SRDS_3
25 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
28 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
29 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
30 int xfi_dpmac[XFI14 + 1];
31 int sgmii_dpmac[SGMII18 + 1];
32 int a25gaui_dpmac[_25GE10 + 1];
33 int xlaui_dpmac[_40GE2 + 1];
34 int caui2_dpmac[_50GE2 + 1];
35 int caui4_dpmac[_100GE2 + 1];
37 int xfi_dpmac[XFI8 + 1];
38 int sgmii_dpmac[SGMII16 + 1];
42 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
48 *The return value of this func is the serdes protocol used.
49 *Typically this function is called number of times depending
50 *upon the number of serdes blocks in the Silicon.
51 *Zero is used to denote that no serdes was enabled,
52 *this is the case when golden RCW was used where DPAA2 bring was
53 *intentionally removed to achieve boot to prompt
56 __weak int serdes_get_number(int serdes, int cfg)
61 int is_serdes_configured(enum srds_prtcl device)
65 #ifdef CONFIG_SYS_FSL_SRDS_1
66 if (!serdes1_prtcl_map[NONE])
69 ret |= serdes1_prtcl_map[device];
71 #ifdef CONFIG_SYS_FSL_SRDS_2
72 if (!serdes2_prtcl_map[NONE])
75 ret |= serdes2_prtcl_map[device];
77 #ifdef CONFIG_SYS_NXP_SRDS_3
78 if (!serdes3_prtcl_map[NONE])
81 ret |= serdes3_prtcl_map[device];
87 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
89 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
94 #ifdef CONFIG_SYS_FSL_SRDS_1
96 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
97 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
98 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
101 #ifdef CONFIG_SYS_FSL_SRDS_2
103 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
104 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
105 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
108 #ifdef CONFIG_SYS_NXP_SRDS_3
110 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
111 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
112 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
116 printf("invalid SerDes%d\n", sd);
120 cfg = serdes_get_number(sd, cfg);
122 /* Is serdes enabled at all? */
126 for (i = 0; i < SRDS_MAX_LANES; i++) {
127 if (serdes_get_prtcl(sd, cfg, i) == device)
134 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
135 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
137 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
141 if (serdes_prtcl_map[NONE])
144 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
146 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
147 cfg >>= sd_prctl_shift;
149 cfg = serdes_get_number(sd, cfg);
151 printf("SERDES%d is disabled\n", sd + 1);
153 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
155 if (!is_serdes_prtcl_valid(sd, cfg))
156 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
159 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
160 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
161 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
162 debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
164 serdes_prtcl_map[lane_prtcl] = 1;
165 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
166 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
167 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
168 wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
171 if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
172 wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
175 if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
176 wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
179 if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
180 wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
183 if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
184 wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
187 if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
188 wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
192 switch (lane_prtcl) {
197 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
200 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
202 xfi_dpmac[lane_prtcl],
205 if (lane_prtcl >= SGMII1 &&
206 lane_prtcl <= SGMII16)
207 wriop_init_dpmac(sd, sgmii_dpmac[
217 /* Set the first element to indicate serdes has been initialized */
218 serdes_prtcl_map[NONE] = 1;
221 __weak int get_serdes_volt(void)
226 __weak int set_serdes_volt(int svdd)
231 #define LNAGCR0_RT_RSTB 0x00600000
233 #define RSTCTL_RESET_MASK 0x000000E0
235 #define RSTCTL_RSTREQ 0x80000000
236 #define RSTCTL_RST_DONE 0x40000000
237 #define RSTCTL_RSTERR 0x20000000
239 #define RSTCTL_SDEN 0x00000020
240 #define RSTCTL_SDRST_B 0x00000040
241 #define RSTCTL_PLLRST_B 0x00000080
243 #define TCALCR_CALRST_B 0x08000000
245 struct serdes_prctl_info {
251 struct serdes_prctl_info srds_prctl_info[] = {
252 #ifdef CONFIG_SYS_FSL_SRDS_1
254 .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
255 .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
259 #ifdef CONFIG_SYS_FSL_SRDS_2
261 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
262 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
265 #ifdef CONFIG_SYS_NXP_SRDS_3
267 .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
268 .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
274 static int get_serdes_prctl_info_idx(u32 serdes_id)
277 struct serdes_prctl_info *srds_info;
279 /* loop until NULL ENTRY defined by .id=0 */
280 for (srds_info = srds_prctl_info; srds_info->id != 0;
281 srds_info++, pos++) {
282 if (srds_info->id == serdes_id)
289 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
290 struct ccsr_serdes __iomem *serdes_base,
296 pos = get_serdes_prctl_info_idx(serdes_id);
298 printf("invalid serdes_id %d\n", serdes_id);
302 cfg_tmp = cfg & srds_prctl_info[pos].mask;
303 cfg_tmp >>= srds_prctl_info[pos].shift;
305 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
307 setbits_le32(&serdes_base->lane[i].gcr0,
310 clrbits_le32(&serdes_base->lane[i].gcr0,
315 static void do_pll_reset(u32 cfg,
316 struct ccsr_serdes __iomem *serdes_base)
320 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
321 clrbits_le32(&serdes_base->bank[i].rstctl,
325 setbits_le32(&serdes_base->bank[i].rstctl,
331 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
333 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
334 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
337 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
338 struct ccsr_serdes __iomem *serdes_base)
340 if (!(cfg == 0x3 && i == 1)) {
342 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
343 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
348 static void do_pll_reset_done(u32 cfg,
349 struct ccsr_serdes __iomem *serdes_base)
354 for (i = 0; i < 2; i++) {
355 reg = in_le32(&serdes_base->bank[i].pllcr0);
356 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
357 setbits_le32(&serdes_base->bank[i].rstctl,
363 static void do_serdes_enable(u32 cfg,
364 struct ccsr_serdes __iomem *serdes_base)
368 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
369 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
372 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
374 /* Take the Rx/Tx calibration out of reset */
375 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
379 static void do_pll_lock(u32 cfg,
380 struct ccsr_serdes __iomem *serdes_base)
385 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
386 /* if the PLL is not locked, set RST_ERR */
387 reg = in_le32(&serdes_base->bank[i].pllcr0);
388 if (!((reg >> 23) & 0x1)) {
389 setbits_le32(&serdes_base->bank[i].rstctl,
393 setbits_le32(&serdes_base->bank[i].rstctl,
400 int setup_serdes_volt(u32 svdd)
402 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
403 struct ccsr_serdes __iomem *serdes1_base =
404 (void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
405 u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
406 #ifdef CONFIG_SYS_FSL_SRDS_2
407 struct ccsr_serdes __iomem *serdes2_base =
408 (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
409 u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
411 #ifdef CONFIG_SYS_NXP_SRDS_3
412 struct ccsr_serdes __iomem *serdes3_base =
413 (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
414 u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
417 int svdd_cur, svdd_tar;
420 /* Only support switch SVDD to 900mV */
424 /* Scale up to the LTC resolution is 1/4096V */
425 svdd = (svdd * 4096) / 1000;
428 svdd_cur = get_serdes_volt();
432 debug("%s: current SVDD: %x; target SVDD: %x\n",
433 __func__, svdd_cur, svdd_tar);
434 if (svdd_cur == svdd_tar)
437 /* Put the all enabled lanes in reset */
438 #ifdef CONFIG_SYS_FSL_SRDS_1
439 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
442 #ifdef CONFIG_SYS_FSL_SRDS_2
443 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
445 #ifdef CONFIG_SYS_NXP_SRDS_3
446 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
449 /* Put the all enabled PLL in reset */
450 #ifdef CONFIG_SYS_FSL_SRDS_1
451 cfg_tmp = cfg_rcwsrds1 & 0x3;
452 do_pll_reset(cfg_tmp, serdes1_base);
455 #ifdef CONFIG_SYS_FSL_SRDS_2
456 cfg_tmp = cfg_rcwsrds1 & 0xC;
458 do_pll_reset(cfg_tmp, serdes2_base);
461 #ifdef CONFIG_SYS_NXP_SRDS_3
462 cfg_tmp = cfg_rcwsrds3 & 0x30;
464 do_pll_reset(cfg_tmp, serdes3_base);
467 /* Put the Rx/Tx calibration into reset */
468 #ifdef CONFIG_SYS_FSL_SRDS_1
469 do_rx_tx_cal_reset(serdes1_base);
472 #ifdef CONFIG_SYS_FSL_SRDS_2
473 do_rx_tx_cal_reset(serdes2_base);
476 #ifdef CONFIG_SYS_NXP_SRDS_3
477 do_rx_tx_cal_reset(serdes3_base);
480 ret = set_serdes_volt(svdd);
482 printf("could not change SVDD\n");
486 /* For each PLL that’s not disabled via RCW enable the SERDES */
487 #ifdef CONFIG_SYS_FSL_SRDS_1
488 cfg_tmp = cfg_rcwsrds1 & 0x3;
489 do_serdes_enable(cfg_tmp, serdes1_base);
491 #ifdef CONFIG_SYS_FSL_SRDS_2
492 cfg_tmp = cfg_rcwsrds1 & 0xC;
494 do_serdes_enable(cfg_tmp, serdes2_base);
496 #ifdef CONFIG_SYS_NXP_SRDS_3
497 cfg_tmp = cfg_rcwsrds3 & 0x30;
499 do_serdes_enable(cfg_tmp, serdes3_base);
502 /* Wait for at at least 625us, ensure the PLLs being reset are locked */
505 #ifdef CONFIG_SYS_FSL_SRDS_1
506 cfg_tmp = cfg_rcwsrds1 & 0x3;
507 do_pll_lock(cfg_tmp, serdes1_base);
510 #ifdef CONFIG_SYS_FSL_SRDS_2
511 cfg_tmp = cfg_rcwsrds1 & 0xC;
513 do_pll_lock(cfg_tmp, serdes2_base);
516 #ifdef CONFIG_SYS_NXP_SRDS_3
517 cfg_tmp = cfg_rcwsrds3 & 0x30;
519 do_pll_lock(cfg_tmp, serdes3_base);
522 /* Take the all enabled lanes out of reset */
523 #ifdef CONFIG_SYS_FSL_SRDS_1
524 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
526 #ifdef CONFIG_SYS_FSL_SRDS_2
527 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
530 #ifdef CONFIG_SYS_NXP_SRDS_3
531 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
534 /* For each PLL being reset, and achieved PLL lock set RST_DONE */
535 #ifdef CONFIG_SYS_FSL_SRDS_1
536 cfg_tmp = cfg_rcwsrds1 & 0x3;
537 do_pll_reset_done(cfg_tmp, serdes1_base);
539 #ifdef CONFIG_SYS_FSL_SRDS_2
540 cfg_tmp = cfg_rcwsrds1 & 0xC;
542 do_pll_reset_done(cfg_tmp, serdes2_base);
545 #ifdef CONFIG_SYS_NXP_SRDS_3
546 cfg_tmp = cfg_rcwsrds3 & 0x30;
548 do_pll_reset_done(cfg_tmp, serdes3_base);
554 void fsl_serdes_init(void)
556 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
559 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
560 for (i = XFI1, j = 1; i <= XFI14; i++, j++)
563 for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
566 for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
567 a25gaui_dpmac[i] = j;
569 for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
572 for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
575 for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
578 for (i = XFI1, j = 1; i <= XFI8; i++, j++)
581 for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
586 #ifdef CONFIG_SYS_FSL_SRDS_1
587 serdes_init(FSL_SRDS_1,
588 CFG_SYS_FSL_LSCH3_SERDES_ADDR,
589 FSL_CHASSIS3_SRDS1_REGSR,
590 FSL_CHASSIS3_SRDS1_PRTCL_MASK,
591 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
594 #ifdef CONFIG_SYS_FSL_SRDS_2
595 serdes_init(FSL_SRDS_2,
596 CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
597 FSL_CHASSIS3_SRDS2_REGSR,
598 FSL_CHASSIS3_SRDS2_PRTCL_MASK,
599 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
602 #ifdef CONFIG_SYS_NXP_SRDS_3
603 serdes_init(NXP_SRDS_3,
604 CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
605 FSL_CHASSIS3_SRDS3_REGSR,
606 FSL_CHASSIS3_SRDS3_PRTCL_MASK,
607 FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
612 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
614 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
615 char scfg[16], snum[16];
619 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
620 cfg >>= sd_prctl_shift;
621 cfg = serdes_get_number(sd, cfg);
623 #if defined(SRDS_BITS_PER_LANE)
625 * reverse lanes, lane 0 should be printed first so it must be moved to
627 * For example bb58 should read 85bb, lane 0 being protocol 8.
628 * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
629 * independent per-lane protocol configuration, at this time LS1028A and
630 * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
631 * lanes as a single value.
633 for (int i = 0; i < SRDS_MAX_LANES; i++) {
636 tmp = cfg >> (i * SRDS_BITS_PER_LANE);
637 tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
638 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
641 #endif /* SRDS_BITS_PER_LANE */
643 snprintf(snum, 16, "serdes%d", sd);
644 snprintf(scfg, 16, "%x", cfgr);
650 int serdes_misc_init(void)
652 #ifdef CONFIG_SYS_FSL_SRDS_1
653 serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
654 FSL_CHASSIS3_SRDS1_PRTCL_MASK,
655 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
657 #ifdef CONFIG_SYS_FSL_SRDS_2
658 serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
659 FSL_CHASSIS3_SRDS2_PRTCL_MASK,
660 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
662 #ifdef CONFIG_SYS_NXP_SRDS_3
663 serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
664 FSL_CHASSIS3_SRDS3_PRTCL_MASK,
665 FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);