1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016-2018 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
9 #include <linux/errno.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
12 #include <fsl-mc/ldpaa_wriop.h>
14 #ifdef CONFIG_SYS_FSL_SRDS_1
15 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
17 #ifdef CONFIG_SYS_FSL_SRDS_2
18 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
20 #ifdef CONFIG_SYS_NXP_SRDS_3
21 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
24 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
25 int xfi_dpmac[XFI8 + 1];
26 int sgmii_dpmac[SGMII16 + 1];
29 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
35 *The return value of this func is the serdes protocol used.
36 *Typically this function is called number of times depending
37 *upon the number of serdes blocks in the Silicon.
38 *Zero is used to denote that no serdes was enabled,
39 *this is the case when golden RCW was used where DPAA2 bring was
40 *intentionally removed to achieve boot to prompt
43 __weak int serdes_get_number(int serdes, int cfg)
48 int is_serdes_configured(enum srds_prtcl device)
52 #ifdef CONFIG_SYS_FSL_SRDS_1
53 if (!serdes1_prtcl_map[NONE])
56 ret |= serdes1_prtcl_map[device];
58 #ifdef CONFIG_SYS_FSL_SRDS_2
59 if (!serdes2_prtcl_map[NONE])
62 ret |= serdes2_prtcl_map[device];
64 #ifdef CONFIG_SYS_NXP_SRDS_3
65 if (!serdes3_prtcl_map[NONE])
68 ret |= serdes3_prtcl_map[device];
74 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
76 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
81 #ifdef CONFIG_SYS_FSL_SRDS_1
83 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
84 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
85 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
88 #ifdef CONFIG_SYS_FSL_SRDS_2
90 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
91 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
92 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
95 #ifdef CONFIG_SYS_NXP_SRDS_3
97 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
98 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
99 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
103 printf("invalid SerDes%d\n", sd);
107 cfg = serdes_get_number(sd, cfg);
109 /* Is serdes enabled at all? */
113 for (i = 0; i < SRDS_MAX_LANES; i++) {
114 if (serdes_get_prtcl(sd, cfg, i) == device)
121 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
122 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
124 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
128 if (serdes_prtcl_map[NONE])
131 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
133 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
134 cfg >>= sd_prctl_shift;
136 cfg = serdes_get_number(sd, cfg);
137 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
139 if (!is_serdes_prtcl_valid(sd, cfg))
140 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
142 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
143 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
144 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
145 debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
147 serdes_prtcl_map[lane_prtcl] = 1;
148 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
149 switch (lane_prtcl) {
154 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
157 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
159 xfi_dpmac[lane_prtcl],
162 if (lane_prtcl >= SGMII1 &&
163 lane_prtcl <= SGMII16)
164 wriop_init_dpmac(sd, sgmii_dpmac[
173 /* Set the first element to indicate serdes has been initialized */
174 serdes_prtcl_map[NONE] = 1;
177 __weak int get_serdes_volt(void)
182 __weak int set_serdes_volt(int svdd)
187 #define LNAGCR0_RT_RSTB 0x00600000
189 #define RSTCTL_RESET_MASK 0x000000E0
191 #define RSTCTL_RSTREQ 0x80000000
192 #define RSTCTL_RST_DONE 0x40000000
193 #define RSTCTL_RSTERR 0x20000000
195 #define RSTCTL_SDEN 0x00000020
196 #define RSTCTL_SDRST_B 0x00000040
197 #define RSTCTL_PLLRST_B 0x00000080
199 #define TCALCR_CALRST_B 0x08000000
201 struct serdes_prctl_info {
207 struct serdes_prctl_info srds_prctl_info[] = {
208 #ifdef CONFIG_SYS_FSL_SRDS_1
210 .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
211 .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
215 #ifdef CONFIG_SYS_FSL_SRDS_2
217 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
218 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
221 #ifdef CONFIG_SYS_NXP_SRDS_3
223 .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
224 .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
230 static int get_serdes_prctl_info_idx(u32 serdes_id)
233 struct serdes_prctl_info *srds_info;
235 /* loop until NULL ENTRY defined by .id=0 */
236 for (srds_info = srds_prctl_info; srds_info->id != 0;
237 srds_info++, pos++) {
238 if (srds_info->id == serdes_id)
245 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
246 struct ccsr_serdes __iomem *serdes_base,
252 pos = get_serdes_prctl_info_idx(serdes_id);
254 printf("invalid serdes_id %d\n", serdes_id);
258 cfg_tmp = cfg & srds_prctl_info[pos].mask;
259 cfg_tmp >>= srds_prctl_info[pos].shift;
261 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
263 setbits_le32(&serdes_base->lane[i].gcr0,
266 clrbits_le32(&serdes_base->lane[i].gcr0,
271 static void do_pll_reset(u32 cfg,
272 struct ccsr_serdes __iomem *serdes_base)
276 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
277 clrbits_le32(&serdes_base->bank[i].rstctl,
281 setbits_le32(&serdes_base->bank[i].rstctl,
287 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
289 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
290 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
293 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
294 struct ccsr_serdes __iomem *serdes_base)
296 if (!(cfg == 0x3 && i == 1)) {
298 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
299 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
304 static void do_pll_reset_done(u32 cfg,
305 struct ccsr_serdes __iomem *serdes_base)
310 for (i = 0; i < 2; i++) {
311 reg = in_le32(&serdes_base->bank[i].pllcr0);
312 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
313 setbits_le32(&serdes_base->bank[i].rstctl,
319 static void do_serdes_enable(u32 cfg,
320 struct ccsr_serdes __iomem *serdes_base)
324 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
325 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
328 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
330 /* Take the Rx/Tx calibration out of reset */
331 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
335 static void do_pll_lock(u32 cfg,
336 struct ccsr_serdes __iomem *serdes_base)
341 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
342 /* if the PLL is not locked, set RST_ERR */
343 reg = in_le32(&serdes_base->bank[i].pllcr0);
344 if (!((reg >> 23) & 0x1)) {
345 setbits_le32(&serdes_base->bank[i].rstctl,
349 setbits_le32(&serdes_base->bank[i].rstctl,
356 int setup_serdes_volt(u32 svdd)
358 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
359 struct ccsr_serdes __iomem *serdes1_base =
360 (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
361 u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
362 #ifdef CONFIG_SYS_FSL_SRDS_2
363 struct ccsr_serdes __iomem *serdes2_base =
364 (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
365 u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
367 #ifdef CONFIG_SYS_NXP_SRDS_3
368 struct ccsr_serdes __iomem *serdes3_base =
369 (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
370 u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
373 int svdd_cur, svdd_tar;
376 /* Only support switch SVDD to 900mV */
380 /* Scale up to the LTC resolution is 1/4096V */
381 svdd = (svdd * 4096) / 1000;
384 svdd_cur = get_serdes_volt();
388 debug("%s: current SVDD: %x; target SVDD: %x\n",
389 __func__, svdd_cur, svdd_tar);
390 if (svdd_cur == svdd_tar)
393 /* Put the all enabled lanes in reset */
394 #ifdef CONFIG_SYS_FSL_SRDS_1
395 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
398 #ifdef CONFIG_SYS_FSL_SRDS_2
399 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
401 #ifdef CONFIG_SYS_NXP_SRDS_3
402 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
405 /* Put the all enabled PLL in reset */
406 #ifdef CONFIG_SYS_FSL_SRDS_1
407 cfg_tmp = cfg_rcwsrds1 & 0x3;
408 do_pll_reset(cfg_tmp, serdes1_base);
411 #ifdef CONFIG_SYS_FSL_SRDS_2
412 cfg_tmp = cfg_rcwsrds1 & 0xC;
414 do_pll_reset(cfg_tmp, serdes2_base);
417 #ifdef CONFIG_SYS_NXP_SRDS_3
418 cfg_tmp = cfg_rcwsrds3 & 0x30;
420 do_pll_reset(cfg_tmp, serdes3_base);
423 /* Put the Rx/Tx calibration into reset */
424 #ifdef CONFIG_SYS_FSL_SRDS_1
425 do_rx_tx_cal_reset(serdes1_base);
428 #ifdef CONFIG_SYS_FSL_SRDS_2
429 do_rx_tx_cal_reset(serdes2_base);
432 #ifdef CONFIG_SYS_NXP_SRDS_3
433 do_rx_tx_cal_reset(serdes3_base);
436 ret = set_serdes_volt(svdd);
438 printf("could not change SVDD\n");
442 /* For each PLL that’s not disabled via RCW enable the SERDES */
443 #ifdef CONFIG_SYS_FSL_SRDS_1
444 cfg_tmp = cfg_rcwsrds1 & 0x3;
445 do_serdes_enable(cfg_tmp, serdes1_base);
447 #ifdef CONFIG_SYS_FSL_SRDS_2
448 cfg_tmp = cfg_rcwsrds1 & 0xC;
450 do_serdes_enable(cfg_tmp, serdes2_base);
452 #ifdef CONFIG_SYS_NXP_SRDS_3
453 cfg_tmp = cfg_rcwsrds3 & 0x30;
455 do_serdes_enable(cfg_tmp, serdes3_base);
458 /* Wait for at at least 625us, ensure the PLLs being reset are locked */
461 #ifdef CONFIG_SYS_FSL_SRDS_1
462 cfg_tmp = cfg_rcwsrds1 & 0x3;
463 do_pll_lock(cfg_tmp, serdes1_base);
466 #ifdef CONFIG_SYS_FSL_SRDS_2
467 cfg_tmp = cfg_rcwsrds1 & 0xC;
469 do_pll_lock(cfg_tmp, serdes2_base);
472 #ifdef CONFIG_SYS_NXP_SRDS_3
473 cfg_tmp = cfg_rcwsrds3 & 0x30;
475 do_pll_lock(cfg_tmp, serdes3_base);
478 /* Take the all enabled lanes out of reset */
479 #ifdef CONFIG_SYS_FSL_SRDS_1
480 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
482 #ifdef CONFIG_SYS_FSL_SRDS_2
483 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
486 #ifdef CONFIG_SYS_NXP_SRDS_3
487 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
490 /* For each PLL being reset, and achieved PLL lock set RST_DONE */
491 #ifdef CONFIG_SYS_FSL_SRDS_1
492 cfg_tmp = cfg_rcwsrds1 & 0x3;
493 do_pll_reset_done(cfg_tmp, serdes1_base);
495 #ifdef CONFIG_SYS_FSL_SRDS_2
496 cfg_tmp = cfg_rcwsrds1 & 0xC;
498 do_pll_reset_done(cfg_tmp, serdes2_base);
501 #ifdef CONFIG_SYS_NXP_SRDS_3
502 cfg_tmp = cfg_rcwsrds3 & 0x30;
504 do_pll_reset_done(cfg_tmp, serdes3_base);
510 void fsl_serdes_init(void)
512 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
515 for (i = XFI1, j = 1; i <= XFI8; i++, j++)
518 for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
522 #ifdef CONFIG_SYS_FSL_SRDS_1
523 serdes_init(FSL_SRDS_1,
524 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
525 FSL_CHASSIS3_SRDS1_REGSR,
526 FSL_CHASSIS3_SRDS1_PRTCL_MASK,
527 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
530 #ifdef CONFIG_SYS_FSL_SRDS_2
531 serdes_init(FSL_SRDS_2,
532 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
533 FSL_CHASSIS3_SRDS2_REGSR,
534 FSL_CHASSIS3_SRDS2_PRTCL_MASK,
535 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
538 #ifdef CONFIG_SYS_NXP_SRDS_3
539 serdes_init(NXP_SRDS_3,
540 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
541 FSL_CHASSIS3_SRDS3_REGSR,
542 FSL_CHASSIS3_SRDS3_PRTCL_MASK,
543 FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,