1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016-2018 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
9 #include <linux/errno.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
12 #include <fsl-mc/ldpaa_wriop.h>
14 #ifdef CONFIG_SYS_FSL_SRDS_1
15 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
17 #ifdef CONFIG_SYS_FSL_SRDS_2
18 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
20 #ifdef CONFIG_SYS_NXP_SRDS_3
21 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
24 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
25 #ifdef CONFIG_ARCH_LX2160A
26 int xfi_dpmac[XFI14 + 1];
27 int sgmii_dpmac[SGMII18 + 1];
28 int a25gaui_dpmac[_25GE10 + 1];
29 int xlaui_dpmac[_40GE2 + 1];
30 int caui2_dpmac[_50GE2 + 1];
31 int caui4_dpmac[_100GE2 + 1];
33 int xfi_dpmac[XFI8 + 1];
34 int sgmii_dpmac[SGMII16 + 1];
38 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
44 *The return value of this func is the serdes protocol used.
45 *Typically this function is called number of times depending
46 *upon the number of serdes blocks in the Silicon.
47 *Zero is used to denote that no serdes was enabled,
48 *this is the case when golden RCW was used where DPAA2 bring was
49 *intentionally removed to achieve boot to prompt
52 __weak int serdes_get_number(int serdes, int cfg)
57 int is_serdes_configured(enum srds_prtcl device)
61 #ifdef CONFIG_SYS_FSL_SRDS_1
62 if (!serdes1_prtcl_map[NONE])
65 ret |= serdes1_prtcl_map[device];
67 #ifdef CONFIG_SYS_FSL_SRDS_2
68 if (!serdes2_prtcl_map[NONE])
71 ret |= serdes2_prtcl_map[device];
73 #ifdef CONFIG_SYS_NXP_SRDS_3
74 if (!serdes3_prtcl_map[NONE])
77 ret |= serdes3_prtcl_map[device];
83 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
85 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
90 #ifdef CONFIG_SYS_FSL_SRDS_1
92 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
93 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
94 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
97 #ifdef CONFIG_SYS_FSL_SRDS_2
99 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
100 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
101 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
104 #ifdef CONFIG_SYS_NXP_SRDS_3
106 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
107 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
108 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
112 printf("invalid SerDes%d\n", sd);
116 cfg = serdes_get_number(sd, cfg);
118 /* Is serdes enabled at all? */
122 for (i = 0; i < SRDS_MAX_LANES; i++) {
123 if (serdes_get_prtcl(sd, cfg, i) == device)
130 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
131 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
133 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
137 if (serdes_prtcl_map[NONE])
140 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
142 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
143 cfg >>= sd_prctl_shift;
145 cfg = serdes_get_number(sd, cfg);
146 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
148 if (!is_serdes_prtcl_valid(sd, cfg))
149 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
151 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
152 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
153 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
154 debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
156 serdes_prtcl_map[lane_prtcl] = 1;
157 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
158 #ifdef CONFIG_ARCH_LX2160A
159 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
160 wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
163 if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
164 wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
167 if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
168 wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
171 if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
172 wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
175 if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
176 wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
179 if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
180 wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
184 switch (lane_prtcl) {
189 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
192 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
194 xfi_dpmac[lane_prtcl],
197 if (lane_prtcl >= SGMII1 &&
198 lane_prtcl <= SGMII16)
199 wriop_init_dpmac(sd, sgmii_dpmac[
209 /* Set the first element to indicate serdes has been initialized */
210 serdes_prtcl_map[NONE] = 1;
213 __weak int get_serdes_volt(void)
218 __weak int set_serdes_volt(int svdd)
223 #define LNAGCR0_RT_RSTB 0x00600000
225 #define RSTCTL_RESET_MASK 0x000000E0
227 #define RSTCTL_RSTREQ 0x80000000
228 #define RSTCTL_RST_DONE 0x40000000
229 #define RSTCTL_RSTERR 0x20000000
231 #define RSTCTL_SDEN 0x00000020
232 #define RSTCTL_SDRST_B 0x00000040
233 #define RSTCTL_PLLRST_B 0x00000080
235 #define TCALCR_CALRST_B 0x08000000
237 struct serdes_prctl_info {
243 struct serdes_prctl_info srds_prctl_info[] = {
244 #ifdef CONFIG_SYS_FSL_SRDS_1
246 .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
247 .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
251 #ifdef CONFIG_SYS_FSL_SRDS_2
253 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
254 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
257 #ifdef CONFIG_SYS_NXP_SRDS_3
259 .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
260 .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
266 static int get_serdes_prctl_info_idx(u32 serdes_id)
269 struct serdes_prctl_info *srds_info;
271 /* loop until NULL ENTRY defined by .id=0 */
272 for (srds_info = srds_prctl_info; srds_info->id != 0;
273 srds_info++, pos++) {
274 if (srds_info->id == serdes_id)
281 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
282 struct ccsr_serdes __iomem *serdes_base,
288 pos = get_serdes_prctl_info_idx(serdes_id);
290 printf("invalid serdes_id %d\n", serdes_id);
294 cfg_tmp = cfg & srds_prctl_info[pos].mask;
295 cfg_tmp >>= srds_prctl_info[pos].shift;
297 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
299 setbits_le32(&serdes_base->lane[i].gcr0,
302 clrbits_le32(&serdes_base->lane[i].gcr0,
307 static void do_pll_reset(u32 cfg,
308 struct ccsr_serdes __iomem *serdes_base)
312 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
313 clrbits_le32(&serdes_base->bank[i].rstctl,
317 setbits_le32(&serdes_base->bank[i].rstctl,
323 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
325 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
326 clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
329 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
330 struct ccsr_serdes __iomem *serdes_base)
332 if (!(cfg == 0x3 && i == 1)) {
334 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
335 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
340 static void do_pll_reset_done(u32 cfg,
341 struct ccsr_serdes __iomem *serdes_base)
346 for (i = 0; i < 2; i++) {
347 reg = in_le32(&serdes_base->bank[i].pllcr0);
348 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
349 setbits_le32(&serdes_base->bank[i].rstctl,
355 static void do_serdes_enable(u32 cfg,
356 struct ccsr_serdes __iomem *serdes_base)
360 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
361 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
364 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
366 /* Take the Rx/Tx calibration out of reset */
367 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
371 static void do_pll_lock(u32 cfg,
372 struct ccsr_serdes __iomem *serdes_base)
377 for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
378 /* if the PLL is not locked, set RST_ERR */
379 reg = in_le32(&serdes_base->bank[i].pllcr0);
380 if (!((reg >> 23) & 0x1)) {
381 setbits_le32(&serdes_base->bank[i].rstctl,
385 setbits_le32(&serdes_base->bank[i].rstctl,
392 int setup_serdes_volt(u32 svdd)
394 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
395 struct ccsr_serdes __iomem *serdes1_base =
396 (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
397 u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
398 #ifdef CONFIG_SYS_FSL_SRDS_2
399 struct ccsr_serdes __iomem *serdes2_base =
400 (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
401 u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
403 #ifdef CONFIG_SYS_NXP_SRDS_3
404 struct ccsr_serdes __iomem *serdes3_base =
405 (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
406 u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
409 int svdd_cur, svdd_tar;
412 /* Only support switch SVDD to 900mV */
416 /* Scale up to the LTC resolution is 1/4096V */
417 svdd = (svdd * 4096) / 1000;
420 svdd_cur = get_serdes_volt();
424 debug("%s: current SVDD: %x; target SVDD: %x\n",
425 __func__, svdd_cur, svdd_tar);
426 if (svdd_cur == svdd_tar)
429 /* Put the all enabled lanes in reset */
430 #ifdef CONFIG_SYS_FSL_SRDS_1
431 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
434 #ifdef CONFIG_SYS_FSL_SRDS_2
435 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
437 #ifdef CONFIG_SYS_NXP_SRDS_3
438 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
441 /* Put the all enabled PLL in reset */
442 #ifdef CONFIG_SYS_FSL_SRDS_1
443 cfg_tmp = cfg_rcwsrds1 & 0x3;
444 do_pll_reset(cfg_tmp, serdes1_base);
447 #ifdef CONFIG_SYS_FSL_SRDS_2
448 cfg_tmp = cfg_rcwsrds1 & 0xC;
450 do_pll_reset(cfg_tmp, serdes2_base);
453 #ifdef CONFIG_SYS_NXP_SRDS_3
454 cfg_tmp = cfg_rcwsrds3 & 0x30;
456 do_pll_reset(cfg_tmp, serdes3_base);
459 /* Put the Rx/Tx calibration into reset */
460 #ifdef CONFIG_SYS_FSL_SRDS_1
461 do_rx_tx_cal_reset(serdes1_base);
464 #ifdef CONFIG_SYS_FSL_SRDS_2
465 do_rx_tx_cal_reset(serdes2_base);
468 #ifdef CONFIG_SYS_NXP_SRDS_3
469 do_rx_tx_cal_reset(serdes3_base);
472 ret = set_serdes_volt(svdd);
474 printf("could not change SVDD\n");
478 /* For each PLL that’s not disabled via RCW enable the SERDES */
479 #ifdef CONFIG_SYS_FSL_SRDS_1
480 cfg_tmp = cfg_rcwsrds1 & 0x3;
481 do_serdes_enable(cfg_tmp, serdes1_base);
483 #ifdef CONFIG_SYS_FSL_SRDS_2
484 cfg_tmp = cfg_rcwsrds1 & 0xC;
486 do_serdes_enable(cfg_tmp, serdes2_base);
488 #ifdef CONFIG_SYS_NXP_SRDS_3
489 cfg_tmp = cfg_rcwsrds3 & 0x30;
491 do_serdes_enable(cfg_tmp, serdes3_base);
494 /* Wait for at at least 625us, ensure the PLLs being reset are locked */
497 #ifdef CONFIG_SYS_FSL_SRDS_1
498 cfg_tmp = cfg_rcwsrds1 & 0x3;
499 do_pll_lock(cfg_tmp, serdes1_base);
502 #ifdef CONFIG_SYS_FSL_SRDS_2
503 cfg_tmp = cfg_rcwsrds1 & 0xC;
505 do_pll_lock(cfg_tmp, serdes2_base);
508 #ifdef CONFIG_SYS_NXP_SRDS_3
509 cfg_tmp = cfg_rcwsrds3 & 0x30;
511 do_pll_lock(cfg_tmp, serdes3_base);
514 /* Take the all enabled lanes out of reset */
515 #ifdef CONFIG_SYS_FSL_SRDS_1
516 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
518 #ifdef CONFIG_SYS_FSL_SRDS_2
519 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
522 #ifdef CONFIG_SYS_NXP_SRDS_3
523 do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
526 /* For each PLL being reset, and achieved PLL lock set RST_DONE */
527 #ifdef CONFIG_SYS_FSL_SRDS_1
528 cfg_tmp = cfg_rcwsrds1 & 0x3;
529 do_pll_reset_done(cfg_tmp, serdes1_base);
531 #ifdef CONFIG_SYS_FSL_SRDS_2
532 cfg_tmp = cfg_rcwsrds1 & 0xC;
534 do_pll_reset_done(cfg_tmp, serdes2_base);
537 #ifdef CONFIG_SYS_NXP_SRDS_3
538 cfg_tmp = cfg_rcwsrds3 & 0x30;
540 do_pll_reset_done(cfg_tmp, serdes3_base);
546 void fsl_serdes_init(void)
548 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
551 #ifdef CONFIG_ARCH_LX2160A
552 for (i = XFI1, j = 1; i <= XFI14; i++, j++)
555 for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
558 for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
559 a25gaui_dpmac[i] = j;
561 for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
564 for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
567 for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
570 for (i = XFI1, j = 1; i <= XFI8; i++, j++)
573 for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
578 #ifdef CONFIG_SYS_FSL_SRDS_1
579 serdes_init(FSL_SRDS_1,
580 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
581 FSL_CHASSIS3_SRDS1_REGSR,
582 FSL_CHASSIS3_SRDS1_PRTCL_MASK,
583 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
586 #ifdef CONFIG_SYS_FSL_SRDS_2
587 serdes_init(FSL_SRDS_2,
588 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
589 FSL_CHASSIS3_SRDS2_REGSR,
590 FSL_CHASSIS3_SRDS2_PRTCL_MASK,
591 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
594 #ifdef CONFIG_SYS_NXP_SRDS_3
595 serdes_init(NXP_SRDS_3,
596 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
597 FSL_CHASSIS3_SRDS3_REGSR,
598 FSL_CHASSIS3_SRDS3_PRTCL_MASK,
599 FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
604 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
606 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
607 char scfg[16], snum[16];
611 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
612 cfg >>= sd_prctl_shift;
613 cfg = serdes_get_number(sd, cfg);
615 #if defined(SRDS_BITS_PER_LANE)
617 * reverse lanes, lane 0 should be printed first so it must be moved to
619 * For example bb58 should read 85bb, lane 0 being protocol 8.
620 * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
621 * independent per-lane protocol configuration, at this time LS1028A and
622 * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
623 * lanes as a single value.
625 for (int i = 0; i < SRDS_MAX_LANES; i++) {
628 tmp = cfg >> (i * SRDS_BITS_PER_LANE);
629 tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
630 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
633 #endif /* SRDS_BITS_PER_LANE */
635 snprintf(snum, 16, "serdes%d", sd);
636 snprintf(scfg, 16, "%x", cfgr);
642 int serdes_misc_init(void)
644 #ifdef CONFIG_SYS_FSL_SRDS_1
645 serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
646 FSL_CHASSIS3_SRDS1_PRTCL_MASK,
647 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
649 #ifdef CONFIG_SYS_FSL_SRDS_2
650 serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
651 FSL_CHASSIS3_SRDS2_PRTCL_MASK,
652 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
654 #ifdef CONFIG_SYS_NXP_SRDS_3
655 serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
656 FSL_CHASSIS3_SRDS3_PRTCL_MASK,
657 FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);