arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP.
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <cpu_func.h>
  10 #include <linux/compiler.h>
  11 #include <asm/io.h>
  12 #include <asm/processor.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/soc.h>
  15 #include <fsl_ifc.h>
  16 #include "cpu.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  21 #define CONFIG_SYS_FSL_NUM_CC_PLLS      2
  22 #endif
  23
  24 void get_sys_info(struct sys_info *sys_info)
  25 {
  26         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  27 /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
  28  * mux 2 clock for LS1043A/LS1046A.
  29  */
  30 #if defined(CONFIG_SYS_DPAA_FMAN) || \
  31             defined(CONFIG_TARGET_LS1046ARDB) || \
  32             defined(CONFIG_TARGET_LS1043ARDB)
  33         u32 rcw_tmp;
  34 #endif
  35         struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
  36         unsigned int cpu;
  37         const u8 core_cplx_pll[8] = {
  38                 [0] = 0,        /* CC1 PPL / 1 */
  39                 [1] = 0,        /* CC1 PPL / 2 */
  40                 [4] = 1,        /* CC2 PPL / 1 */
  41                 [5] = 1,        /* CC2 PPL / 2 */
  42         };
  43
  44         const u8 core_cplx_pll_div[8] = {
  45                 [0] = 1,        /* CC1 PPL / 1 */
  46                 [1] = 2,        /* CC1 PPL / 2 */
  47                 [4] = 1,        /* CC2 PPL / 1 */
  48                 [5] = 2,        /* CC2 PPL / 2 */
  49         };
  50
  51         uint i, cluster;
  52         uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  53         uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  54         unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  55         unsigned long cluster_clk;
  56
  57         sys_info->freq_systembus = sysclk;
  58 #ifndef CONFIG_CLUSTER_CLK_FREQ
  59 #define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
  60 #endif
  61         cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
  62
  63 #ifdef CONFIG_DDR_CLK_FREQ
  64         sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  65 #else
  66         sys_info->freq_ddrbus = sysclk;
  67 #endif
  68
  69         /* The freq_systembus is used to record frequency of platform PLL */
  70         sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
  71                         FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
  72                         FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
  73
  74 #ifdef CONFIG_ARCH_LS1012A
  75         sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
  76 #else
  77         sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  78                         FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
  79                         FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
  80 #endif
  81
  82         for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
  83                 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
  84                 if (ratio[i] > 4)
  85                         freq_c_pll[i] = cluster_clk * ratio[i];
  86                 else
  87                         freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
  88         }
  89
  90         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  91                 cluster = fsl_qoriq_core_to_cluster(cpu);
  92                 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
  93                                 & 0xf;
  94                 u32 cplx_pll = core_cplx_pll[c_pll_sel];
  95
  96                 sys_info->freq_processor[cpu] =
  97                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  98         }
  99
 100 #define HWA_CGA_M1_CLK_SEL      0xe0000000
 101 #define HWA_CGA_M1_CLK_SHIFT    29
 102 #ifdef CONFIG_SYS_DPAA_FMAN
 103         rcw_tmp = in_be32(&gur->rcwsr[7]);
 104         switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
 105         case 2:
 106                 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
 107                 break;
 108         case 3:
 109                 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
 110                 break;
 111         case 4:
 112                 sys_info->freq_fman[0] = freq_c_pll[0] / 4;
 113                 break;
 114         case 5:
 115                 sys_info->freq_fman[0] = sys_info->freq_systembus;
 116                 break;
 117         case 6:
 118                 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
 119                 break;
 120         case 7:
 121                 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
 122                 break;
 123         default:
 124                 printf("Error: Unknown FMan1 clock select!\n");
 125                 break;
 126         }
 127 #endif
 128
 129 #define HWA_CGA_M2_CLK_SEL      0x00000007
 130 #define HWA_CGA_M2_CLK_SHIFT    0
 131 #if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
 132         rcw_tmp = in_be32(&gur->rcwsr[15]);
 133         switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
 134         case 1:
 135                 sys_info->freq_cga_m2 = freq_c_pll[1];
 136                 break;
 137 #if defined(CONFIG_TARGET_LS1046ARDB)
 138         case 2:
 139                 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
 140                 break;
 141 #endif
 142         case 3:
 143                 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
 144                 break;
 145 #if defined(CONFIG_TARGET_LS1046ARDB)
 146         case 6:
 147                 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
 148                 break;
 149 #endif
 150         default:
 151                 printf("Error: Unknown cluster group A mux 2 clock select!\n");
 152                 break;
 153         }
 154 #endif
 155
 156 #if defined(CONFIG_FSL_IFC)
 157         sys_info->freq_localbus = sys_info->freq_systembus /
 158                                                 CONFIG_SYS_FSL_IFC_CLK_DIV;
 159 #endif
 160 #ifdef CONFIG_SYS_DPAA_QBMAN
 161         sys_info->freq_qman = (sys_info->freq_systembus /
 162                                 CONFIG_SYS_FSL_PCLK_DIV) /
 163                                 CONFIG_SYS_FSL_QMAN_CLK_DIV;
 164 #endif
 165 }
 166
 167 #ifdef CONFIG_SYS_DPAA_QBMAN
 168 unsigned long get_qman_freq(void)
 169 {
 170         struct sys_info sys_info;
 171
 172         get_sys_info(&sys_info);
 173
 174         return sys_info.freq_qman;
 175 }
 176 #endif
 177
 178 int get_clocks(void)
 179 {
 180         struct sys_info sys_info;
 181 #ifdef CONFIG_FSL_ESDHC
 182         u32 clock = 0;
 183 #endif
 184         get_sys_info(&sys_info);
 185         gd->cpu_clk = sys_info.freq_processor[0];
 186         gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
 187         gd->mem_clk = sys_info.freq_ddrbus;
 188 #ifdef CONFIG_FSL_ESDHC
 189 #if defined(CONFIG_ARCH_LS1012A)
 190         clock = sys_info.freq_systembus;
 191 #elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 192         clock = sys_info.freq_cga_m2;
 193 #endif
 194         gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 195         gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 196 #endif
 197         if (gd->cpu_clk != 0)
 198                 return 0;
 199         else
 200                 return 1;
 201 }
 202
 203 /********************************************
 204  * get_bus_freq
 205  * return platform clock in Hz
 206  *********************************************/
 207 ulong get_bus_freq(ulong dummy)
 208 {
 209         if (!gd->bus_clk)
 210                 get_clocks();
 211
 212         return gd->bus_clk;
 213 }
 214
 215 ulong get_ddr_freq(ulong dummy)
 216 {
 217         if (!gd->mem_clk)
 218                 get_clocks();
 219
 220         return gd->mem_clk;
 221 }
 222
 223 int get_serial_clock(void)
 224 {
 225         return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
 226 }
 227
 228 int get_i2c_freq(ulong dummy)
 229 {
 230         return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
 231 }
 232
 233 int get_dspi_freq(ulong dummy)
 234 {
 235         return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
 236 }
 237
 238 #ifdef CONFIG_FSL_LPUART
 239 int get_uart_freq(ulong dummy)
 240 {
 241         return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
 242 }
 243 #endif
 244
 245 unsigned int mxc_get_clock(enum mxc_clock clk)
 246 {
 247         switch (clk) {
 248         case MXC_I2C_CLK:
 249                 return get_i2c_freq(0);
 250         case MXC_DSPI_CLK:
 251                 return get_dspi_freq(0);
 252 #ifdef CONFIG_FSL_LPUART
 253         case MXC_UART_CLK:
 254                 return get_uart_freq(0);
 255 #endif
 256         default:
 257                 printf("Unsupported clock\n");
 258         }
 259         return 0;
 260 }