2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/compiler.h>
10 #include <asm/processor.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/soc.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
18 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
21 void get_sys_info(struct sys_info *sys_info)
23 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
25 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
28 #ifdef CONFIG_SYS_DPAA_FMAN
31 struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
33 const u8 core_cplx_pll[8] = {
34 [0] = 0, /* CC1 PPL / 1 */
35 [1] = 0, /* CC1 PPL / 2 */
36 [4] = 1, /* CC2 PPL / 1 */
37 [5] = 1, /* CC2 PPL / 2 */
40 const u8 core_cplx_pll_div[8] = {
41 [0] = 1, /* CC1 PPL / 1 */
42 [1] = 2, /* CC1 PPL / 2 */
43 [4] = 1, /* CC2 PPL / 1 */
44 [5] = 2, /* CC2 PPL / 2 */
48 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
49 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
50 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
52 sys_info->freq_systembus = sysclk;
53 #ifdef CONFIG_DDR_CLK_FREQ
54 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
56 sys_info->freq_ddrbus = sysclk;
59 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
60 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
61 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
62 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
63 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
64 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
66 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
67 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
69 freq_c_pll[i] = sysclk * ratio[i];
71 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
74 for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
75 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
77 u32 cplx_pll = core_cplx_pll[c_pll_sel];
79 sys_info->freq_processor[cpu] =
80 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
83 #define HWA_CGA_M1_CLK_SEL 0xe0000000
84 #define HWA_CGA_M1_CLK_SHIFT 29
85 #ifdef CONFIG_SYS_DPAA_FMAN
86 rcw_tmp = in_be32(&gur->rcwsr[7]);
87 switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
89 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
92 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
95 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
98 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
101 printf("Error: Unknown FMan1 clock select!\n");
106 #define HWA_CGA_M2_CLK_SEL 0x00000007
107 #define HWA_CGA_M2_CLK_SHIFT 0
109 #if defined(CONFIG_FSL_IFC)
110 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
111 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
113 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
119 struct sys_info sys_info;
121 get_sys_info(&sys_info);
122 gd->cpu_clk = sys_info.freq_processor[0];
123 gd->bus_clk = sys_info.freq_systembus;
124 gd->mem_clk = sys_info.freq_ddrbus;
126 if (gd->cpu_clk != 0)
132 ulong get_bus_freq(ulong dummy)
137 ulong get_ddr_freq(ulong dummy)
142 int get_serial_clock(void)
147 unsigned int mxc_get_clock(enum mxc_clock clk)
151 return get_bus_freq(0);
153 return get_bus_freq(0);
155 return get_bus_freq(0);
157 printf("Unsupported clock\n");