2 # Copyright 2014-2015 Freescale Semiconductor
4 # SPDX-License-Identifier: GPL-2.0+
7 Freescale LayerScape with Chassis Generation 3
9 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
14 Entire DDR region splits into two regions.
15 - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
16 - Region 2 is at 0x80_8000_0000 to the top of total memory,
17 for example 16GB, 0x83_ffff_ffff.
19 All DDR memory is marked as cache-enabled.
21 When MC and Debug server is enabled, they carve 512MB away from the high
22 end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
23 with MC and Debug server enabled. Linux only sees 15.5GB.
25 The reserved 512MB layout looks like
27 +---------------+ <-- top/end of memory
28 | 256MB | debug server
34 MC requires the memory to be aligned with 512MB, so even debug server is
35 not enabled, 512MB is reserved, not 256MB.
40 (1) A typical layout of various images (including Linux and other firmware images)
41 is shown below considering a 32MB NOR flash device present on most
42 pre-silicon platforms (simulator and emulator):
44 -------------------------
46 | (linux + DTB + RFS) |
47 ------------------------- ----> 0x0120_0000
49 ------------------------- ----> 0x00C0_0000
51 ------------------------- ----> 0x0070_0000
53 ------------------------- ----> 0x006C_0000
55 ------------------------- ----> 0x0020_0000
57 ------------------------- ----> 0x0000_1000
59 ------------------------- ----> 0x0000_0080
61 ------------------------- ----> 0x0000_0000
63 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
65 (2) A typical layout of various images (including Linux and other firmware images)
66 is shown below considering a 128MB NOR flash device present on QDS and RDB
68 ----------------------------------------- ----> 0x5_8800_0000 ---
69 | .. Unused .. (7M) | |
70 ----------------------------------------- ----> 0x5_8790_0000 |
71 | FIT Image (linux + DTB + RFS) (40M) | |
72 ----------------------------------------- ----> 0x5_8510_0000 |
73 | PHY firmware (2M) | |
74 ----------------------------------------- ----> 0x5_84F0_0000 | 64K
75 | Debug Server FW (2M) | | Alt
76 ----------------------------------------- ----> 0x5_84D0_0000 | Bank
78 ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
79 | MC DPC Blob (1M) | |
80 ----------------------------------------- ----> 0x5_8480_0000 |
81 | MC DPL Blob (1M) | |
82 ----------------------------------------- ----> 0x5_8470_0000 |
84 ----------------------------------------- ----> 0x5_8430_0000 |
85 | BootLoader Environment (1M) | |
86 ----------------------------------------- ----> 0x5_8420_0000 |
88 ----------------------------------------- ----> 0x5_8410_0000 |
89 | RCW and PBI (1M) | |
90 ----------------------------------------- ----> 0x5_8400_0000 ---
91 | .. Unused .. (7M) | |
92 ----------------------------------------- ----> 0x5_8390_0000 |
93 | FIT Image (linux + DTB + RFS) (40M) | |
94 ----------------------------------------- ----> 0x5_8110_0000 |
95 | PHY firmware (2M) | |
96 ----------------------------------------- ----> 0x5_80F0_0000 | 64K
97 | Debug Server FW (2M) | | Bank
98 ----------------------------------------- ----> 0x5_80D0_0000 |
100 ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
101 | MC DPC Blob (1M) | |
102 ----------------------------------------- ----> 0x5_8080_0000 |
103 | MC DPL Blob (1M) | |
104 ----------------------------------------- ----> 0x5_8070_0000 |
106 ----------------------------------------- ----> 0x5_8030_0000 |
107 | BootLoader Environment (1M) | |
108 ----------------------------------------- ----> 0x5_8020_0000 |
109 | BootLoader (1M) | |
110 ----------------------------------------- ----> 0x5_8010_0000 |
111 | RCW and PBI (1M) | |
112 ----------------------------------------- ----> 0x5_8000_0000 ---
114 128-MB NOR flash layout for QDS and RDB boards
116 Environment Variables
117 =====================
118 mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
119 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
121 mcmemsize: MC DRAM block size. If this variable is not defined, the value
122 CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
126 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
127 The difference between NAND boot RCW image and NOR boot image is the PBI
128 command sequence. Below is one example for PBI commands for QDS which uses
129 NAND device with 2KB/page, block size 128KB.
131 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
132 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
133 The above two commands set bootloc register to 0x00000000_1800a000 where
134 the u-boot code will be running in OCRAM.
136 3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
137 BLOCK_SIZE=0x00014000
138 This command copies u-boot image from NAND device into OCRAM. The values need
139 to adjust accordingly.
141 SRC should match the cfg_rcw_src, the reset config pins. It depends
142 on the NAND device. See reference manual for cfg_rcw_src.
143 SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
144 the example above, 128KB. For easy maintenance, we put it at
145 the beginning of next block from RCW.
146 DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
147 BLOCK_SIZE is the size to be copied by PBI.
149 RCW image should be written to the beginning of NAND device. Example of using
152 nand write <rcw image in memory> 0 <size of rcw image>
154 To form the NAND image, build u-boot with NAND config, for example,
155 ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
156 The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
158 nand write <u-boot image in memory> 200000 <size of u-boot image>
160 With these two images in NAND device, the board can boot from NAND.
162 Another example for RDB boards,
164 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
165 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
166 3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
167 BLOCK_SIZE=0x00014000
169 nand write <rcw image in memory> 0 <size of rcw image>
170 nand write <u-boot image in memory> 80000 <size of u-boot image>
172 Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
173 to match board NAND device with 4KB/page, block size 512KB.
175 MMU Translation Tables
176 ======================
178 (1) Early MMU Tables:
180 Level 0 Level 1 Level 2
181 ------------------ ------------------ ------------------
182 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
183 ------------------ ------------------ ------------------
184 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
185 ------------------ | ------------------ ------------------
186 | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
187 ------------------ | ------------------ ------------------
188 | | 0x00_c000_0000 | | 0x00_0060_0000 |
189 | ------------------ ------------------
190 | | 0x01_0000_0000 | | 0x00_0080_0000 |
191 | ------------------ ------------------
194 | | 0x05_8000_0000 | --|
195 | ------------------ |
196 | | 0x05_c000_0000 | |
197 | ------------------ |
199 | ------------------ | ------------------
200 |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 |
201 ------------------ ------------------
202 | 0x80_4000_0000 | | 0x00_3020_0000 |
203 ------------------ ------------------
204 | 0x80_8000_0000 | | 0x00_3040_0000 |
205 ------------------ ------------------
206 | 0x80_c000_0000 | | 0x00_3060_0000 |
207 ------------------ ------------------
208 | 0x81_0000_0000 | | 0x00_3080_0000 |
209 ------------------ ------------------
212 (2) Final MMU Tables:
214 Level 0 Level 1 Level 2
215 ------------------ ------------------ ------------------
216 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
217 ------------------ ------------------ ------------------
218 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
219 ------------------ | ------------------ ------------------
220 | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
221 ------------------ | ------------------ ------------------
222 | | 0x00_c000_0000 | | 0x00_0060_0000 |
223 | ------------------ ------------------
224 | | 0x01_0000_0000 | | 0x00_0080_0000 |
225 | ------------------ ------------------
228 | | 0x08_0000_0000 | --|
229 | ------------------ |
230 | | 0x08_4000_0000 | |
231 | ------------------ |
233 | ------------------ | ------------------
234 |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 |
235 ------------------ ------------------
236 | 0x80_4000_0000 | | 0x08_0020_0000 |
237 ------------------ ------------------
238 | 0x80_8000_0000 | | 0x08_0040_0000 |
239 ------------------ ------------------
240 | 0x80_c000_0000 | | 0x08_0060_0000 |
241 ------------------ ------------------
242 | 0x81_0000_0000 | | 0x08_0080_0000 |
243 ------------------ ------------------
247 DPAA2 commands to manage Management Complex (MC)
248 ------------------------------------------------
249 DPAA2 commands has been introduced to manage Management Complex
250 (MC). These commands are used to start mc, aiop and apply DPL
251 from u-boot command prompt.
253 Please note Management complex Firmware(MC), DPL and DPC are no
254 more deployed during u-boot boot-sequence.
257 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
258 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
259 c) fsl_mc start aiop <FW_addr> - Start AIOP
261 How to use commands :-
262 1. Command sequence for u-boot ethernet:
263 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
264 b) DPMAC net-devices are now available for use
267 Assumption: MC firmware, DPL and DPC dtb is already programmed
270 => fsl_mc start mc 580300000 580800000
271 => setenv ethact DPMAC1@xgmii
274 2. Command sequence for Linux boot:
275 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
276 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
277 c) No DPMAC net-devices are available for use in u-boot
281 Assumption: MC firmware, DPL and DPC dtb is already programmed
284 => fsl_mc start mc 580300000 580800000
285 => setenv ethact DPMAC1@xgmii
286 => tftp a0000000 kernel.itb
287 => fsl_mc apply dpl 580700000
290 3. Command sequence for AIOP boot:
291 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
292 b) fsl_mc start aiop <FW_addr> - Start AIOP
293 c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
294 d) No DPMAC net-devices are availabe for use in u-boot
295 Please note actual AIOP start will happen during DPL parsing of
299 Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
300 programmed on NOR flash.
302 => fsl_mc start mc 580300000 580800000
303 => fsl_mc start aiop 0x580900000
304 => setenv ethact DPMAC1@xgmii
305 => fsl_mc apply dpl 580700000
309 If the core runs at higher than x3 speed of the platform, there is
310 possiblity about sev instruction to getting missed by other cores.
311 This is because of SoC Run Control block may not able to sample
312 the EVENTI(Sev) signals.
314 Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
317 Errata workaround uses Env variable "a009635_interval_val". It uses decimal
319 - Default value of env variable is platform clock (MHz)
321 - User can modify default value by updating the env variable
322 setenv a009635_interval_val 600; saveenv;
323 It configure platform clock as 600 MHz
325 - Env variable as 0 signifies no workaround