1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2019 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
10 #include <fsl_ddr_sdram.h>
14 #include <linux/errno.h>
15 #include <asm/system.h>
17 #include <asm/armv8/mmu.h>
19 #include <asm/arch/fsl_serdes.h>
20 #include <asm/arch/soc.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/speed.h>
23 #include <fsl_immap.h>
24 #include <asm/arch/mp.h>
25 #include <efi_loader.h>
26 #include <fsl-mc/fsl_mc.h>
27 #ifdef CONFIG_FSL_ESDHC
28 #include <fsl_esdhc.h>
30 #include <asm/armv8/sec_firmware.h>
31 #ifdef CONFIG_SYS_FSL_DDR
34 #include <asm/arch/clock.h>
36 #include <fsl_qbman.h>
39 #include <env_internal.h>
40 #ifdef CONFIG_CHAIN_OF_TRUST
41 #include <fsl_validate.h>
44 #include <linux/mii.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 static struct cpu_type cpu_type_list[] = {
49 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
50 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
51 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
52 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
53 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
54 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
55 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
56 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
57 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
58 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
59 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
60 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
61 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
62 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
63 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
64 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
65 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
66 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
67 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
68 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
69 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
70 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
71 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
72 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
73 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
74 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
75 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
76 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
79 #define EARLY_PGTABLE_SIZE 0x5000
80 static struct mm_region early_map[] = {
81 #ifdef CONFIG_FSL_LSCH3
82 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
83 CONFIG_SYS_FSL_CCSR_SIZE,
84 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
85 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
87 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
88 SYS_FSL_OCRAM_SPACE_SIZE,
89 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
91 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
92 CONFIG_SYS_FSL_QSPI_SIZE1,
93 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
95 /* For IFC Region #1, only the first 4MB is cache-enabled */
96 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
97 CONFIG_SYS_FSL_IFC_SIZE1_1,
98 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
100 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
101 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
102 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
103 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
105 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
106 CONFIG_SYS_FSL_IFC_SIZE1,
107 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
110 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
111 CONFIG_SYS_FSL_DRAM_SIZE1,
112 #if defined(CONFIG_TFABOOT) || \
113 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
114 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
115 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
116 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
118 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
120 #ifdef CONFIG_FSL_IFC
121 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
122 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
123 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
124 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
127 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
128 CONFIG_SYS_FSL_DCSR_SIZE,
129 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
130 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
132 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
133 CONFIG_SYS_FSL_DRAM_SIZE2,
134 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
135 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
137 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
138 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
139 CONFIG_SYS_FSL_DRAM_SIZE3,
140 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
141 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
144 #elif defined(CONFIG_FSL_LSCH2)
145 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
146 CONFIG_SYS_FSL_CCSR_SIZE,
147 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
148 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
150 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
151 SYS_FSL_OCRAM_SPACE_SIZE,
152 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
154 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
155 CONFIG_SYS_FSL_DCSR_SIZE,
156 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
157 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
159 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
160 CONFIG_SYS_FSL_QSPI_SIZE,
161 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
163 #ifdef CONFIG_FSL_IFC
164 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
165 CONFIG_SYS_FSL_IFC_SIZE,
166 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
169 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
170 CONFIG_SYS_FSL_DRAM_SIZE1,
171 #if defined(CONFIG_TFABOOT) || \
172 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
173 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
174 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
175 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
177 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
179 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
180 CONFIG_SYS_FSL_DRAM_SIZE2,
181 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
182 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
185 {}, /* list terminator */
188 static struct mm_region final_map[] = {
189 #ifdef CONFIG_FSL_LSCH3
190 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
191 CONFIG_SYS_FSL_CCSR_SIZE,
192 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
193 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
195 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
196 SYS_FSL_OCRAM_SPACE_SIZE,
197 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
199 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
200 CONFIG_SYS_FSL_DRAM_SIZE1,
201 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
202 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
204 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
205 CONFIG_SYS_FSL_QSPI_SIZE1,
206 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
207 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
209 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
210 CONFIG_SYS_FSL_QSPI_SIZE2,
211 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
212 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
214 #ifdef CONFIG_FSL_IFC
215 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
216 CONFIG_SYS_FSL_IFC_SIZE2,
217 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
218 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
221 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
222 CONFIG_SYS_FSL_DCSR_SIZE,
223 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
224 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
226 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
227 CONFIG_SYS_FSL_MC_SIZE,
228 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
229 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
231 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
232 CONFIG_SYS_FSL_NI_SIZE,
233 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
234 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
236 /* For QBMAN portal, only the first 64MB is cache-enabled */
237 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
238 CONFIG_SYS_FSL_QBMAN_SIZE_1,
239 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
240 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
242 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
243 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
244 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
245 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
246 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
248 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
249 CONFIG_SYS_PCIE1_PHYS_SIZE,
250 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
251 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
253 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
254 CONFIG_SYS_PCIE2_PHYS_SIZE,
255 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
256 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
258 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
259 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
260 CONFIG_SYS_PCIE3_PHYS_SIZE,
261 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
262 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
265 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
266 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
267 CONFIG_SYS_PCIE4_PHYS_SIZE,
268 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
269 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
272 #ifdef SYS_PCIE5_PHYS_ADDR
273 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
275 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
276 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
279 #ifdef SYS_PCIE6_PHYS_ADDR
280 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
282 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
283 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
286 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
287 CONFIG_SYS_FSL_WRIOP1_SIZE,
288 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
289 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
291 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
292 CONFIG_SYS_FSL_AIOP1_SIZE,
293 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
294 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
296 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
297 CONFIG_SYS_FSL_PEBUF_SIZE,
298 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
299 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
301 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
302 CONFIG_SYS_FSL_DRAM_SIZE2,
303 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
304 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
306 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
307 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
308 CONFIG_SYS_FSL_DRAM_SIZE3,
309 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
310 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
313 #elif defined(CONFIG_FSL_LSCH2)
314 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
315 CONFIG_SYS_FSL_BOOTROM_SIZE,
316 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
317 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
319 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
320 CONFIG_SYS_FSL_CCSR_SIZE,
321 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
322 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
324 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
325 SYS_FSL_OCRAM_SPACE_SIZE,
326 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
328 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
329 CONFIG_SYS_FSL_DCSR_SIZE,
330 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
331 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
333 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
334 CONFIG_SYS_FSL_QSPI_SIZE,
335 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
336 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
338 #ifdef CONFIG_FSL_IFC
339 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
340 CONFIG_SYS_FSL_IFC_SIZE,
341 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
344 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
345 CONFIG_SYS_FSL_DRAM_SIZE1,
346 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
347 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
349 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
350 CONFIG_SYS_FSL_QBMAN_SIZE,
351 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
352 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
354 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
355 CONFIG_SYS_FSL_DRAM_SIZE2,
356 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
357 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
359 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
360 CONFIG_SYS_PCIE1_PHYS_SIZE,
361 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
362 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
364 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
365 CONFIG_SYS_PCIE2_PHYS_SIZE,
366 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
367 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
369 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
370 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
371 CONFIG_SYS_PCIE3_PHYS_SIZE,
372 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
373 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
376 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
377 CONFIG_SYS_FSL_DRAM_SIZE3,
378 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
379 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
382 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
383 {}, /* space holder for secure mem */
388 struct mm_region *mem_map = early_map;
390 void cpu_name(char *name)
392 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
393 unsigned int i, svr, ver;
395 svr = gur_in32(&gur->svr);
396 ver = SVR_SOC_VER(svr);
398 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
399 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
400 strcpy(name, cpu_type_list[i].name);
401 #ifdef CONFIG_ARCH_LX2160A
402 if (IS_C_PROCESSOR(svr))
406 if (IS_E_PROCESSOR(svr))
409 sprintf(name + strlen(name), " Rev%d.%d",
410 SVR_MAJ(svr), SVR_MIN(svr));
414 if (i == ARRAY_SIZE(cpu_type_list))
415 strcpy(name, "unknown");
418 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
420 * To start MMU before DDR is available, we create MMU table in SRAM.
421 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
422 * levels of translation tables here to cover 40-bit address space.
423 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
424 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
425 * Note, the debug print in cache_v8.c is not usable for debugging
426 * these early MMU tables because UART is not yet available.
428 static inline void early_mmu_setup(void)
430 unsigned int el = current_el();
432 /* global data is already setup, no allocation yet */
434 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
436 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
437 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
438 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
440 /* Create early page tables */
443 /* point TTBR to the new table */
444 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
445 get_tcr(el, NULL, NULL) &
446 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
449 set_sctlr(get_sctlr() | CR_M);
452 static void fix_pcie_mmu_map(void)
454 #ifdef CONFIG_ARCH_LS2080A
457 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
459 svr = gur_in32(&gur->svr);
460 ver = SVR_SOC_VER(svr);
462 /* Fix PCIE base and size for LS2088A */
463 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
464 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
465 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
466 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
467 switch (final_map[i].phys) {
468 case CONFIG_SYS_PCIE1_PHYS_ADDR:
469 final_map[i].phys = 0x2000000000ULL;
470 final_map[i].virt = 0x2000000000ULL;
471 final_map[i].size = 0x800000000ULL;
473 case CONFIG_SYS_PCIE2_PHYS_ADDR:
474 final_map[i].phys = 0x2800000000ULL;
475 final_map[i].virt = 0x2800000000ULL;
476 final_map[i].size = 0x800000000ULL;
478 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
479 case CONFIG_SYS_PCIE3_PHYS_ADDR:
480 final_map[i].phys = 0x3000000000ULL;
481 final_map[i].virt = 0x3000000000ULL;
482 final_map[i].size = 0x800000000ULL;
485 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
486 case CONFIG_SYS_PCIE4_PHYS_ADDR:
487 final_map[i].phys = 0x3800000000ULL;
488 final_map[i].virt = 0x3800000000ULL;
489 final_map[i].size = 0x800000000ULL;
501 * The final tables look similar to early tables, but different in detail.
502 * These tables are in DRAM. Sub tables are added to enable cache for
505 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
506 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
508 static inline void final_mmu_setup(void)
510 u64 tlb_addr_save = gd->arch.tlb_addr;
511 unsigned int el = current_el();
514 /* fix the final_map before filling in the block entries */
519 /* Update mapping for DDR to actual size */
520 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
522 * Find the entry for DDR mapping and update the address and
523 * size. Zero-sized mapping will be skipped when creating MMU
526 switch (final_map[index].virt) {
527 case CONFIG_SYS_FSL_DRAM_BASE1:
528 final_map[index].virt = gd->bd->bi_dram[0].start;
529 final_map[index].phys = gd->bd->bi_dram[0].start;
530 final_map[index].size = gd->bd->bi_dram[0].size;
532 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
533 case CONFIG_SYS_FSL_DRAM_BASE2:
534 #if (CONFIG_NR_DRAM_BANKS >= 2)
535 final_map[index].virt = gd->bd->bi_dram[1].start;
536 final_map[index].phys = gd->bd->bi_dram[1].start;
537 final_map[index].size = gd->bd->bi_dram[1].size;
539 final_map[index].size = 0;
543 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
544 case CONFIG_SYS_FSL_DRAM_BASE3:
545 #if (CONFIG_NR_DRAM_BANKS >= 3)
546 final_map[index].virt = gd->bd->bi_dram[2].start;
547 final_map[index].phys = gd->bd->bi_dram[2].start;
548 final_map[index].size = gd->bd->bi_dram[2].size;
550 final_map[index].size = 0;
559 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
560 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
563 * Only use gd->arch.secure_ram if the address is
564 * recalculated. Align to 4KB for MMU table.
566 /* put page tables in secure ram */
567 index = ARRAY_SIZE(final_map) - 2;
568 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
569 final_map[index].virt = gd->arch.secure_ram & ~0x3;
570 final_map[index].phys = final_map[index].virt;
571 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
572 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
573 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
574 tlb_addr_save = gd->arch.tlb_addr;
576 /* Use allocated (board_f.c) memory for TLB */
577 tlb_addr_save = gd->arch.tlb_allocated;
578 gd->arch.tlb_addr = tlb_addr_save;
583 /* Reset the fill ptr */
584 gd->arch.tlb_fillptr = tlb_addr_save;
586 /* Create normal system page tables */
589 /* Create emergency page tables */
590 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
591 gd->arch.tlb_emerg = gd->arch.tlb_addr;
593 gd->arch.tlb_addr = tlb_addr_save;
595 /* Disable cache and MMU */
596 dcache_disable(); /* TLBs are invalidated */
597 invalidate_icache_all();
599 /* point TTBR to the new table */
600 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
603 set_sctlr(get_sctlr() | CR_M);
606 u64 get_page_table_size(void)
611 int arch_cpu_init(void)
614 * This function is called before U-Boot relocates itself to speed up
615 * on system running. It is not necessary to run if performance is not
616 * critical. Skip if MMU is already enabled by SPL or other means.
618 if (get_sctlr() & CR_M)
622 __asm_invalidate_dcache_all();
623 __asm_invalidate_tlb_all();
625 set_sctlr(get_sctlr() | CR_C);
635 * This function is called from common/board_r.c.
636 * It recreates MMU table in main memory.
638 void enable_caches(void)
641 __asm_invalidate_tlb_all();
645 #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
647 #ifdef CONFIG_TFABOOT
648 enum boot_src __get_boot_src(u32 porsr1)
650 enum boot_src src = BOOT_SOURCE_RESERVED;
651 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
652 #if !defined(CONFIG_NXP_LSCH3_2)
655 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
657 #if defined(CONFIG_FSL_LSCH3)
658 #if defined(CONFIG_NXP_LSCH3_2)
660 case RCW_SRC_SDHC1_VAL:
661 src = BOOT_SOURCE_SD_MMC;
663 case RCW_SRC_SDHC2_VAL:
664 src = BOOT_SOURCE_SD_MMC2;
666 case RCW_SRC_I2C1_VAL:
667 src = BOOT_SOURCE_I2C1_EXTENDED;
669 case RCW_SRC_FLEXSPI_NAND2K_VAL:
670 src = BOOT_SOURCE_XSPI_NAND;
672 case RCW_SRC_FLEXSPI_NAND4K_VAL:
673 src = BOOT_SOURCE_XSPI_NAND;
675 case RCW_SRC_RESERVED_1_VAL:
676 src = BOOT_SOURCE_RESERVED;
678 case RCW_SRC_FLEXSPI_NOR_24B:
679 src = BOOT_SOURCE_XSPI_NOR;
682 src = BOOT_SOURCE_RESERVED;
685 val = rcw_src & RCW_SRC_TYPE_MASK;
686 if (val == RCW_SRC_NOR_VAL) {
687 val = rcw_src & NOR_TYPE_MASK;
692 src = BOOT_SOURCE_IFC_NOR;
695 src = BOOT_SOURCE_RESERVED;
698 /* RCW SRC Serial Flash */
699 val = rcw_src & RCW_SRC_SERIAL_MASK;
701 case RCW_SRC_QSPI_VAL:
702 /* RCW SRC Serial NOR (QSPI) */
703 src = BOOT_SOURCE_QSPI_NOR;
705 case RCW_SRC_SD_CARD_VAL:
706 /* RCW SRC SD Card */
707 src = BOOT_SOURCE_SD_MMC;
709 case RCW_SRC_EMMC_VAL:
711 src = BOOT_SOURCE_SD_MMC;
713 case RCW_SRC_I2C1_VAL:
714 /* RCW SRC I2C1 Extended */
715 src = BOOT_SOURCE_I2C1_EXTENDED;
718 src = BOOT_SOURCE_RESERVED;
722 #elif defined(CONFIG_FSL_LSCH2)
724 val = rcw_src & RCW_SRC_NAND_MASK;
725 if (val == RCW_SRC_NAND_VAL) {
726 val = rcw_src & NAND_RESERVED_MASK;
727 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
728 src = BOOT_SOURCE_IFC_NAND;
732 val = rcw_src & RCW_SRC_NOR_MASK;
733 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
734 src = BOOT_SOURCE_IFC_NOR;
739 src = BOOT_SOURCE_QSPI_NOR;
742 src = BOOT_SOURCE_SD_MMC;
745 src = BOOT_SOURCE_RESERVED;
751 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
752 src = BOOT_SOURCE_QSPI_NOR;
754 debug("%s: src 0x%x\n", __func__, src);
758 enum boot_src get_boot_src(void)
763 #if defined(CONFIG_FSL_LSCH3)
764 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
765 #elif defined(CONFIG_FSL_LSCH2)
766 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
769 if (current_el() == 2) {
770 regs.regs[0] = SIP_SVC_RCW;
774 porsr1 = regs.regs[1];
777 if (current_el() == 3 || !porsr1) {
778 #ifdef CONFIG_FSL_LSCH3
779 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
780 #elif defined(CONFIG_FSL_LSCH2)
781 porsr1 = in_be32(&gur->porsr1);
785 debug("%s: porsr1 0x%x\n", __func__, porsr1);
787 return __get_boot_src(porsr1);
790 #ifdef CONFIG_ENV_IS_IN_MMC
791 int mmc_get_env_dev(void)
793 enum boot_src src = get_boot_src();
794 int dev = CONFIG_SYS_MMC_ENV_DEV;
797 case BOOT_SOURCE_SD_MMC:
800 case BOOT_SOURCE_SD_MMC2:
811 enum env_location env_get_location(enum env_operation op, int prio)
813 enum boot_src src = get_boot_src();
814 enum env_location env_loc = ENVL_NOWHERE;
819 #ifdef CONFIG_ENV_IS_NOWHERE
824 case BOOT_SOURCE_IFC_NOR:
825 env_loc = ENVL_FLASH;
827 case BOOT_SOURCE_QSPI_NOR:
829 case BOOT_SOURCE_XSPI_NOR:
830 env_loc = ENVL_SPI_FLASH;
832 case BOOT_SOURCE_IFC_NAND:
834 case BOOT_SOURCE_QSPI_NAND:
836 case BOOT_SOURCE_XSPI_NAND:
839 case BOOT_SOURCE_SD_MMC:
841 case BOOT_SOURCE_SD_MMC2:
844 case BOOT_SOURCE_I2C1_EXTENDED:
852 #endif /* CONFIG_TFABOOT */
854 u32 initiator_type(u32 cluster, int init_id)
856 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
857 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
860 type = gur_in32(&gur->tp_ityp[idx]);
861 if (type & TP_ITYP_AV)
867 u32 cpu_pos_mask(void)
869 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
871 u32 cluster, type, mask = 0;
876 cluster = gur_in32(&gur->tp_cluster[i].lower);
877 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
878 type = initiator_type(cluster, j);
879 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
880 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
883 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
890 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
891 int i = 0, count = 0;
892 u32 cluster, type, mask = 0;
897 cluster = gur_in32(&gur->tp_cluster[i].lower);
898 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
899 type = initiator_type(cluster, j);
901 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
907 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
913 * Return the number of cores on this SOC.
915 int cpu_numcores(void)
917 return hweight32(cpu_mask());
920 int fsl_qoriq_core_to_cluster(unsigned int core)
922 struct ccsr_gur __iomem *gur =
923 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
924 int i = 0, count = 0;
930 cluster = gur_in32(&gur->tp_cluster[i].lower);
931 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
932 if (initiator_type(cluster, j)) {
939 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
941 return -1; /* cannot identify the cluster */
944 u32 fsl_qoriq_core_to_type(unsigned int core)
946 struct ccsr_gur __iomem *gur =
947 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
948 int i = 0, count = 0;
954 cluster = gur_in32(&gur->tp_cluster[i].lower);
955 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
956 type = initiator_type(cluster, j);
964 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
966 return -1; /* cannot identify the cluster */
969 #ifndef CONFIG_FSL_LSCH3
972 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
974 return gur_in32(&gur->svr);
978 #ifdef CONFIG_DISPLAY_CPUINFO
979 int print_cpuinfo(void)
981 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
982 struct sys_info sysinfo;
984 unsigned int i, core;
985 u32 type, rcw, svr = gur_in32(&gur->svr);
990 printf(" %s (0x%x)\n", buf, svr);
991 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
992 get_sys_info(&sysinfo);
993 puts("Clock Configuration:");
994 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
997 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
998 printf("CPU%d(%s):%-4s MHz ", core,
999 type == TY_ITYP_VER_A7 ? "A7 " :
1000 (type == TY_ITYP_VER_A53 ? "A53" :
1001 (type == TY_ITYP_VER_A57 ? "A57" :
1002 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
1003 strmhz(buf, sysinfo.freq_processor[core]));
1005 /* Display platform clock as Bus frequency. */
1006 printf("\n Bus: %-4s MHz ",
1007 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1008 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1009 #ifdef CONFIG_SYS_DPAA_FMAN
1010 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1012 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1013 if (soc_has_dp_ddr()) {
1014 printf(" DP-DDR: %-4s MT/s",
1015 strmhz(buf, sysinfo.freq_ddrbus2));
1021 * Display the RCW, so that no one gets confused as to what RCW
1022 * we're actually using for this boot.
1024 puts("Reset Configuration Word (RCW):");
1025 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1026 rcw = gur_in32(&gur->rcwsr[i]);
1028 printf("\n %08x:", i * 4);
1029 printf(" %08x", rcw);
1037 #ifdef CONFIG_FSL_ESDHC
1038 int cpu_mmc_init(bd_t *bis)
1040 return fsl_esdhc_mmc_init(bis);
1044 int cpu_eth_init(bd_t *bis)
1048 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1049 error = fsl_mc_ldpaa_init(bis);
1051 #ifdef CONFIG_FMAN_ENET
1052 fm_standard_init(bis);
1057 static inline int check_psci(void)
1059 unsigned int psci_ver;
1061 psci_ver = sec_firmware_support_psci_version();
1062 if (psci_ver == PSCI_INVALID_VER)
1068 static void config_core_prefetch(void)
1071 char buffer[HWCONFIG_BUFFER_SIZE];
1072 const char *prefetch_arg = NULL;
1075 struct pt_regs regs;
1077 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1082 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1086 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1088 printf("Core0 prefetch can't be disabled\n");
1092 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1093 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1094 regs.regs[1] = mask;
1098 printf("Prefetch disable config failed for mask ");
1100 printf("Prefetch disable config passed for mask ");
1101 printf("0x%x\n", mask);
1105 #ifdef CONFIG_PCIE_ECAM_GENERIC
1106 __weak void set_ecam_icids(void)
1111 int arch_early_init_r(void)
1113 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1116 * erratum A009635 is valid only for LS2080A SoC and
1117 * its personalitiesi
1119 svr_dev_id = get_svr();
1120 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1123 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1124 erratum_a009942_check_cpo();
1127 debug("PSCI: PSCI does not exist.\n");
1129 /* if PSCI does not exist, boot secondary cores here */
1130 if (fsl_layerscape_wake_seconday_cores())
1131 printf("Did not wake secondary cores\n");
1134 config_core_prefetch();
1136 #ifdef CONFIG_SYS_HAS_SERDES
1139 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1140 /* some dpmacs in armv8a based freescale layerscape SOCs can be
1141 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1142 * EC*_PMUX(rgmii) bits in RCW.
1143 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1144 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1145 * Now if a dpmac is enabled by serdes bits then it takes precedence
1146 * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1147 * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1148 * then the dpmac is SGMII and not RGMII.
1150 * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1151 * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1152 * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1153 * then don't enable it.
1157 #ifdef CONFIG_FMAN_ENET
1160 #ifdef CONFIG_SYS_DPAA_QBMAN
1161 setup_qbman_portals();
1163 #ifdef CONFIG_PCIE_ECAM_GENERIC
1169 int timer_init(void)
1171 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1172 #ifdef CONFIG_FSL_LSCH3
1173 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1175 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1176 defined(CONFIG_ARCH_LS1028A)
1177 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1180 #ifdef COUNTER_FREQUENCY_REAL
1181 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1183 /* Update with accurate clock frequency */
1184 if (current_el() == 3)
1185 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1188 #ifdef CONFIG_FSL_LSCH3
1189 /* Enable timebase for all clusters.
1190 * It is safe to do so even some clusters are not enabled.
1192 out_le32(cltbenr, 0xf);
1195 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1196 defined(CONFIG_ARCH_LS1028A)
1198 * In certain Layerscape SoCs, the clock for each core's
1199 * has an enable bit in the PMU Physical Core Time Base Enable
1200 * Register (PCTBENR), which allows the watchdog to operate.
1202 setbits_le32(pctbenr, 0xff);
1204 * For LS2080A SoC and its personalities, timer controller
1205 * offset is different
1207 svr_dev_id = get_svr();
1208 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1209 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1213 /* Enable clock for timer
1214 * This is a global setting.
1216 out_le32(cntcr, 0x1);
1221 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1223 void __efi_runtime reset_cpu(ulong addr)
1227 #ifdef CONFIG_ARCH_LX2160A
1228 val = in_le32(rstcr);
1230 out_le32(rstcr, val);
1232 /* Raise RESET_REQ_B */
1233 val = scfg_in32(rstcr);
1235 scfg_out32(rstcr, val);
1239 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1241 void __efi_runtime EFIAPI efi_reset_system(
1242 enum efi_reset_type reset_type,
1243 efi_status_t reset_status,
1244 unsigned long data_size, void *reset_data)
1246 switch (reset_type) {
1247 case EFI_RESET_COLD:
1248 case EFI_RESET_WARM:
1249 case EFI_RESET_PLATFORM_SPECIFIC:
1252 case EFI_RESET_SHUTDOWN:
1253 /* Nothing we can do */
1260 efi_status_t efi_reset_system_init(void)
1262 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1268 * Calculate reserved memory with given memory bank
1269 * Return aligned memory size on success
1270 * Return (ram_size + needed size) for failure
1272 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1274 phys_size_t ram_top = ram_size;
1276 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1277 ram_top = mc_get_dram_block_size();
1278 if (ram_top > ram_size)
1279 return ram_size + ram_top;
1281 ram_top = ram_size - ram_top;
1282 /* The start address of MC reserved memory needs to be aligned. */
1283 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1286 return ram_size - ram_top;
1289 phys_size_t get_effective_memsize(void)
1291 phys_size_t ea_size, rem = 0;
1294 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1295 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1296 * allocated from first region. If the memory extends to the second
1297 * region (or the third region if applicable), Management Complex (MC)
1298 * memory should be put into the highest region, i.e. the end of DDR
1299 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1300 * U-Boot doesn't relocate itself into higher address. Should DDR be
1301 * configured to skip the first region, this function needs to be
1304 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1305 ea_size = CONFIG_MAX_MEM_MAPPED;
1306 rem = gd->ram_size - ea_size;
1308 ea_size = gd->ram_size;
1311 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1312 /* Check if we have enough space for secure memory */
1313 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1314 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1316 printf("Error: No enough space for secure memory.\n");
1318 /* Check if we have enough memory for MC */
1319 if (rem < board_reserve_ram_top(rem)) {
1320 /* Not enough memory in high region to reserve */
1321 if (ea_size > board_reserve_ram_top(ea_size))
1322 ea_size -= board_reserve_ram_top(ea_size);
1324 printf("Error: No enough space for reserved memory.\n");
1330 #ifdef CONFIG_TFABOOT
1331 phys_size_t tfa_get_dram_size(void)
1333 struct pt_regs regs;
1334 phys_size_t dram_size = 0;
1336 regs.regs[0] = SMC_DRAM_BANK_INFO;
1343 dram_size = regs.regs[1];
1347 static int tfa_dram_init_banksize(void)
1350 struct pt_regs regs;
1351 phys_size_t dram_size = tfa_get_dram_size();
1353 debug("dram_size %llx\n", dram_size);
1359 regs.regs[0] = SMC_DRAM_BANK_INFO;
1368 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1370 gd->bd->bi_dram[i].start = regs.regs[1];
1371 gd->bd->bi_dram[i].size = regs.regs[2];
1373 dram_size -= gd->bd->bi_dram[i].size;
1376 } while (dram_size);
1381 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1382 /* Assign memory for MC */
1383 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1384 if (gd->bd->bi_dram[2].size >=
1385 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1386 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1387 gd->bd->bi_dram[2].size -
1388 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1392 if (gd->bd->bi_dram[1].size >=
1393 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1394 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1395 gd->bd->bi_dram[1].size -
1396 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1397 } else if (gd->bd->bi_dram[0].size >
1398 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1399 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1400 gd->bd->bi_dram[0].size -
1401 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1404 #endif /* CONFIG_FSL_MC_ENET */
1410 int dram_init_banksize(void)
1412 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1413 phys_size_t dp_ddr_size;
1416 #ifdef CONFIG_TFABOOT
1417 if (!tfa_dram_init_banksize())
1421 * gd->ram_size has the total size of DDR memory, less reserved secure
1422 * memory. The DDR extends from low region to high region(s) presuming
1423 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1424 * the location of secure memory. gd->arch.resv_ram tracks the location
1425 * of reserved memory for Management Complex (MC). Because gd->ram_size
1426 * is reduced by this function if secure memory is reserved, checking
1427 * gd->arch.secure_ram should be done to avoid running it repeatedly.
1430 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1431 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1432 debug("No need to run again, skip %s\n", __func__);
1438 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1439 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1440 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1441 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1442 gd->bd->bi_dram[1].size = gd->ram_size -
1443 CONFIG_SYS_DDR_BLOCK1_SIZE;
1444 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1445 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1446 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1447 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1448 CONFIG_SYS_DDR_BLOCK2_SIZE;
1449 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1453 gd->bd->bi_dram[0].size = gd->ram_size;
1455 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1456 if (gd->bd->bi_dram[0].size >
1457 CONFIG_SYS_MEM_RESERVE_SECURE) {
1458 gd->bd->bi_dram[0].size -=
1459 CONFIG_SYS_MEM_RESERVE_SECURE;
1460 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1461 gd->bd->bi_dram[0].size;
1462 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1463 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1465 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1467 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1468 /* Assign memory for MC */
1469 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1470 if (gd->bd->bi_dram[2].size >=
1471 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1472 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1473 gd->bd->bi_dram[2].size -
1474 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1478 if (gd->bd->bi_dram[1].size >=
1479 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1480 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1481 gd->bd->bi_dram[1].size -
1482 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1483 } else if (gd->bd->bi_dram[0].size >
1484 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1485 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1486 gd->bd->bi_dram[0].size -
1487 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1490 #endif /* CONFIG_FSL_MC_ENET */
1492 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1493 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1494 #error "This SoC shouldn't have DP DDR"
1496 if (soc_has_dp_ddr()) {
1497 /* initialize DP-DDR here */
1500 * DDR controller use 0 as the base address for binding.
1501 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1503 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1505 CONFIG_DP_DDR_NUM_CTRLS,
1506 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1509 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1510 gd->bd->bi_dram[2].size = dp_ddr_size;
1512 puts("Not detected");
1517 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1518 debug("%s is called. gd->ram_size is reduced to %lu\n",
1519 __func__, (ulong)gd->ram_size);
1525 #if CONFIG_IS_ENABLED(EFI_LOADER)
1526 void efi_add_known_memory(void)
1529 phys_addr_t ram_start, start;
1530 phys_size_t ram_size;
1534 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1535 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1536 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1537 #error "This SoC shouldn't have DP DDR"
1540 continue; /* skip DP-DDR */
1542 ram_start = gd->bd->bi_dram[i].start;
1543 ram_size = gd->bd->bi_dram[i].size;
1544 #ifdef CONFIG_RESV_RAM
1545 if (gd->arch.resv_ram >= ram_start &&
1546 gd->arch.resv_ram < ram_start + ram_size)
1547 ram_size = gd->arch.resv_ram - ram_start;
1549 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1550 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1552 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1559 * Before DDR size is known, early MMU table have DDR mapped as device memory
1560 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1561 * needs to be set for these mappings.
1562 * If a special case configures DDR with holes in the mapping, the holes need
1563 * to be marked as invalid. This is not implemented in this function.
1565 void update_early_mmu_table(void)
1567 if (!gd->arch.tlb_addr)
1570 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1571 mmu_change_region_attr(
1572 CONFIG_SYS_SDRAM_BASE,
1574 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1575 PTE_BLOCK_OUTER_SHARE |
1579 mmu_change_region_attr(
1580 CONFIG_SYS_SDRAM_BASE,
1581 CONFIG_SYS_DDR_BLOCK1_SIZE,
1582 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1583 PTE_BLOCK_OUTER_SHARE |
1586 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1587 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1588 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1590 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1591 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1592 mmu_change_region_attr(
1593 CONFIG_SYS_DDR_BLOCK2_BASE,
1594 CONFIG_SYS_DDR_BLOCK2_SIZE,
1595 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1596 PTE_BLOCK_OUTER_SHARE |
1599 mmu_change_region_attr(
1600 CONFIG_SYS_DDR_BLOCK3_BASE,
1602 CONFIG_SYS_DDR_BLOCK1_SIZE -
1603 CONFIG_SYS_DDR_BLOCK2_SIZE,
1604 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1605 PTE_BLOCK_OUTER_SHARE |
1611 mmu_change_region_attr(
1612 CONFIG_SYS_DDR_BLOCK2_BASE,
1614 CONFIG_SYS_DDR_BLOCK1_SIZE,
1615 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1616 PTE_BLOCK_OUTER_SHARE |
1623 __weak int dram_init(void)
1626 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1627 defined(CONFIG_SPL_BUILD)
1628 /* This will break-before-make MMU for DDR */
1629 update_early_mmu_table();