arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <hang.h>
  13 #include <net.h>
  14 #include <vsprintf.h>
  15 #include <asm/cache.h>
  16 #include <asm/io.h>
  17 #include <linux/errno.h>
  18 #include <asm/system.h>
  19 #include <fm_eth.h>
  20 #include <asm/armv8/mmu.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/fsl_serdes.h>
  23 #include <asm/arch/soc.h>
  24 #include <asm/arch/cpu.h>
  25 #include <asm/arch/speed.h>
  26 #include <fsl_immap.h>
  27 #include <asm/arch/mp.h>
  28 #include <efi_loader.h>
  29 #include <fsl-mc/fsl_mc.h>
  30 #ifdef CONFIG_FSL_ESDHC
  31 #include <fsl_esdhc.h>
  32 #endif
  33 #include <asm/armv8/sec_firmware.h>
  34 #ifdef CONFIG_SYS_FSL_DDR
  35 #include <fsl_ddr.h>
  36 #endif
  37 #include <asm/arch/clock.h>
  38 #include <hwconfig.h>
  39 #include <fsl_qbman.h>
  40
  41 #ifdef CONFIG_TFABOOT
  42 #include <env_internal.h>
  43 #ifdef CONFIG_CHAIN_OF_TRUST
  44 #include <fsl_validate.h>
  45 #endif
  46 #endif
  47 #include <linux/mii.h>
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 static struct cpu_type cpu_type_list[] = {
  52         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  53         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  54         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  55         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  56         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  57         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  58         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  59         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  60         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  61         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  62         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  63         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  64         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  65         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  66         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  67         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  68         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  69         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  70         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  71         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  72         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  73         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  74         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  75         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  76         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  77         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  78         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  79         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  80 };
  81
  82 #define EARLY_PGTABLE_SIZE 0x5000
  83 static struct mm_region early_map[] = {
  84 #ifdef CONFIG_FSL_LSCH3
  85         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  86           CONFIG_SYS_FSL_CCSR_SIZE,
  87           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  88           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  89         },
  90         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  91           SYS_FSL_OCRAM_SPACE_SIZE,
  92           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  93         },
  94         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  95           CONFIG_SYS_FSL_QSPI_SIZE1,
  96           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  97 #ifdef CONFIG_FSL_IFC
  98         /* For IFC Region #1, only the first 4MB is cache-enabled */
  99         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 100           CONFIG_SYS_FSL_IFC_SIZE1_1,
 101           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 102         },
 103         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 104           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 105           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 106           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 107         },
 108         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 109           CONFIG_SYS_FSL_IFC_SIZE1,
 110           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 111         },
 112 #endif
 113         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 114           CONFIG_SYS_FSL_DRAM_SIZE1,
 115 #if defined(CONFIG_TFABOOT) || \
 116         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 117           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 118 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 119           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 120 #endif
 121           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 122         },
 123 #ifdef CONFIG_FSL_IFC
 124         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 125         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 126           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 127           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 128         },
 129 #endif
 130         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 131           CONFIG_SYS_FSL_DCSR_SIZE,
 132           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 133           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 134         },
 135         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 136           CONFIG_SYS_FSL_DRAM_SIZE2,
 137           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 138           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 139         },
 140 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 141         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 142           CONFIG_SYS_FSL_DRAM_SIZE3,
 143           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 144           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 145         },
 146 #endif
 147 #elif defined(CONFIG_FSL_LSCH2)
 148         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 149           CONFIG_SYS_FSL_CCSR_SIZE,
 150           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 151           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 152         },
 153         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 154           SYS_FSL_OCRAM_SPACE_SIZE,
 155           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 156         },
 157         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 158           CONFIG_SYS_FSL_DCSR_SIZE,
 159           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 160           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 161         },
 162         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 163           CONFIG_SYS_FSL_QSPI_SIZE,
 164           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 165         },
 166 #ifdef CONFIG_FSL_IFC
 167         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 168           CONFIG_SYS_FSL_IFC_SIZE,
 169           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 170         },
 171 #endif
 172         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 173           CONFIG_SYS_FSL_DRAM_SIZE1,
 174 #if defined(CONFIG_TFABOOT) || \
 175         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 176           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 177 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 178           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 179 #endif
 180           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 181         },
 182         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 183           CONFIG_SYS_FSL_DRAM_SIZE2,
 184           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 185           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 186         },
 187 #endif
 188         {},     /* list terminator */
 189 };
 190
 191 static struct mm_region final_map[] = {
 192 #ifdef CONFIG_FSL_LSCH3
 193         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 194           CONFIG_SYS_FSL_CCSR_SIZE,
 195           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 196           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 197         },
 198         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 199           SYS_FSL_OCRAM_SPACE_SIZE,
 200           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 201         },
 202         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 203           CONFIG_SYS_FSL_DRAM_SIZE1,
 204           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 205           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 206         },
 207         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 208           CONFIG_SYS_FSL_QSPI_SIZE1,
 209           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 210           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 211         },
 212         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 213           CONFIG_SYS_FSL_QSPI_SIZE2,
 214           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 215           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 216         },
 217 #ifdef CONFIG_FSL_IFC
 218         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 219           CONFIG_SYS_FSL_IFC_SIZE2,
 220           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 221           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 222         },
 223 #endif
 224         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 225           CONFIG_SYS_FSL_DCSR_SIZE,
 226           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 227           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 228         },
 229         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 230           CONFIG_SYS_FSL_MC_SIZE,
 231           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 232           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 233         },
 234         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 235           CONFIG_SYS_FSL_NI_SIZE,
 236           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 237           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 238         },
 239         /* For QBMAN portal, only the first 64MB is cache-enabled */
 240         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 241           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 242           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 243           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 244         },
 245         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 246           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 247           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 248           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 249           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 250         },
 251         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 252           CONFIG_SYS_PCIE1_PHYS_SIZE,
 253           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 254           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 255         },
 256         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 257           CONFIG_SYS_PCIE2_PHYS_SIZE,
 258           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 259           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 260         },
 261 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 262         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 263           CONFIG_SYS_PCIE3_PHYS_SIZE,
 264           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 265           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 266         },
 267 #endif
 268 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 269         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 270           CONFIG_SYS_PCIE4_PHYS_SIZE,
 271           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 272           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 273         },
 274 #endif
 275 #ifdef SYS_PCIE5_PHYS_ADDR
 276         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 277           SYS_PCIE5_PHYS_SIZE,
 278           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 279           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 280         },
 281 #endif
 282 #ifdef SYS_PCIE6_PHYS_ADDR
 283         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 284           SYS_PCIE6_PHYS_SIZE,
 285           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 286           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 287         },
 288 #endif
 289         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 290           CONFIG_SYS_FSL_WRIOP1_SIZE,
 291           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 292           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 293         },
 294         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 295           CONFIG_SYS_FSL_AIOP1_SIZE,
 296           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 297           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 298         },
 299         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 300           CONFIG_SYS_FSL_PEBUF_SIZE,
 301           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 302           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 303         },
 304         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 305           CONFIG_SYS_FSL_DRAM_SIZE2,
 306           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 307           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 308         },
 309 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 310         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 311           CONFIG_SYS_FSL_DRAM_SIZE3,
 312           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 313           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 314         },
 315 #endif
 316 #elif defined(CONFIG_FSL_LSCH2)
 317         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 318           CONFIG_SYS_FSL_BOOTROM_SIZE,
 319           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 320           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 321         },
 322         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 323           CONFIG_SYS_FSL_CCSR_SIZE,
 324           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 325           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 326         },
 327         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 328           SYS_FSL_OCRAM_SPACE_SIZE,
 329           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 330         },
 331         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 332           CONFIG_SYS_FSL_DCSR_SIZE,
 333           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 334           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 335         },
 336         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 337           CONFIG_SYS_FSL_QSPI_SIZE,
 338           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 339           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 340         },
 341 #ifdef CONFIG_FSL_IFC
 342         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 343           CONFIG_SYS_FSL_IFC_SIZE,
 344           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 345         },
 346 #endif
 347         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 348           CONFIG_SYS_FSL_DRAM_SIZE1,
 349           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 350           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 351         },
 352         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 353           CONFIG_SYS_FSL_QBMAN_SIZE,
 354           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 355           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 356         },
 357         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 358           CONFIG_SYS_FSL_DRAM_SIZE2,
 359           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 360           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 361         },
 362         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 363           CONFIG_SYS_PCIE1_PHYS_SIZE,
 364           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 365           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 366         },
 367         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 368           CONFIG_SYS_PCIE2_PHYS_SIZE,
 369           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 370           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 371         },
 372 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 373         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 374           CONFIG_SYS_PCIE3_PHYS_SIZE,
 375           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 376           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 377         },
 378 #endif
 379         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 380           CONFIG_SYS_FSL_DRAM_SIZE3,
 381           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 382           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 383         },
 384 #endif
 385 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 386         {},     /* space holder for secure mem */
 387 #endif
 388         {},
 389 };
 390
 391 struct mm_region *mem_map = early_map;
 392
 393 void cpu_name(char *name)
 394 {
 395         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 396         unsigned int i, svr, ver;
 397
 398         svr = gur_in32(&gur->svr);
 399         ver = SVR_SOC_VER(svr);
 400
 401         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 402                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 403                         strcpy(name, cpu_type_list[i].name);
 404 #ifdef CONFIG_ARCH_LX2160A
 405                         if (IS_C_PROCESSOR(svr))
 406                                 strcat(name, "C");
 407 #endif
 408
 409                         if (IS_E_PROCESSOR(svr))
 410                                 strcat(name, "E");
 411
 412                         sprintf(name + strlen(name), " Rev%d.%d",
 413                                 SVR_MAJ(svr), SVR_MIN(svr));
 414                         break;
 415                 }
 416
 417         if (i == ARRAY_SIZE(cpu_type_list))
 418                 strcpy(name, "unknown");
 419 }
 420
 421 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 422 /*
 423  * To start MMU before DDR is available, we create MMU table in SRAM.
 424  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 425  * levels of translation tables here to cover 40-bit address space.
 426  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 427  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 428  * Note, the debug print in cache_v8.c is not usable for debugging
 429  * these early MMU tables because UART is not yet available.
 430  */
 431 static inline void early_mmu_setup(void)
 432 {
 433         unsigned int el = current_el();
 434
 435         /* global data is already setup, no allocation yet */
 436         if (el == 3)
 437                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 438         else
 439                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 440         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 441         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 442
 443         /* Create early page tables */
 444         setup_pgtables();
 445
 446         /* point TTBR to the new table */
 447         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 448                           get_tcr(el, NULL, NULL) &
 449                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 450                           MEMORY_ATTRIBUTES);
 451
 452         set_sctlr(get_sctlr() | CR_M);
 453 }
 454
 455 static void fix_pcie_mmu_map(void)
 456 {
 457 #ifdef CONFIG_ARCH_LS2080A
 458         unsigned int i;
 459         u32 svr, ver;
 460         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 461
 462         svr = gur_in32(&gur->svr);
 463         ver = SVR_SOC_VER(svr);
 464
 465         /* Fix PCIE base and size for LS2088A */
 466         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 467             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 468             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 469                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 470                         switch (final_map[i].phys) {
 471                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 472                                 final_map[i].phys = 0x2000000000ULL;
 473                                 final_map[i].virt = 0x2000000000ULL;
 474                                 final_map[i].size = 0x800000000ULL;
 475                                 break;
 476                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 477                                 final_map[i].phys = 0x2800000000ULL;
 478                                 final_map[i].virt = 0x2800000000ULL;
 479                                 final_map[i].size = 0x800000000ULL;
 480                                 break;
 481 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 482                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 483                                 final_map[i].phys = 0x3000000000ULL;
 484                                 final_map[i].virt = 0x3000000000ULL;
 485                                 final_map[i].size = 0x800000000ULL;
 486                                 break;
 487 #endif
 488 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 489                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 490                                 final_map[i].phys = 0x3800000000ULL;
 491                                 final_map[i].virt = 0x3800000000ULL;
 492                                 final_map[i].size = 0x800000000ULL;
 493                                 break;
 494 #endif
 495                         default:
 496                                 break;
 497                         }
 498                 }
 499         }
 500 #endif
 501 }
 502
 503 /*
 504  * The final tables look similar to early tables, but different in detail.
 505  * These tables are in DRAM. Sub tables are added to enable cache for
 506  * QBMan and OCRAM.
 507  *
 508  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 509  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 510  */
 511 static inline void final_mmu_setup(void)
 512 {
 513         u64 tlb_addr_save = gd->arch.tlb_addr;
 514         unsigned int el = current_el();
 515         int index;
 516
 517         /* fix the final_map before filling in the block entries */
 518         fix_pcie_mmu_map();
 519
 520         mem_map = final_map;
 521
 522         /* Update mapping for DDR to actual size */
 523         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 524                 /*
 525                  * Find the entry for DDR mapping and update the address and
 526                  * size. Zero-sized mapping will be skipped when creating MMU
 527                  * table.
 528                  */
 529                 switch (final_map[index].virt) {
 530                 case CONFIG_SYS_FSL_DRAM_BASE1:
 531                         final_map[index].virt = gd->bd->bi_dram[0].start;
 532                         final_map[index].phys = gd->bd->bi_dram[0].start;
 533                         final_map[index].size = gd->bd->bi_dram[0].size;
 534                         break;
 535 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 536                 case CONFIG_SYS_FSL_DRAM_BASE2:
 537 #if (CONFIG_NR_DRAM_BANKS >= 2)
 538                         final_map[index].virt = gd->bd->bi_dram[1].start;
 539                         final_map[index].phys = gd->bd->bi_dram[1].start;
 540                         final_map[index].size = gd->bd->bi_dram[1].size;
 541 #else
 542                         final_map[index].size = 0;
 543 #endif
 544                 break;
 545 #endif
 546 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 547                 case CONFIG_SYS_FSL_DRAM_BASE3:
 548 #if (CONFIG_NR_DRAM_BANKS >= 3)
 549                         final_map[index].virt = gd->bd->bi_dram[2].start;
 550                         final_map[index].phys = gd->bd->bi_dram[2].start;
 551                         final_map[index].size = gd->bd->bi_dram[2].size;
 552 #else
 553                         final_map[index].size = 0;
 554 #endif
 555                 break;
 556 #endif
 557                 default:
 558                         break;
 559                 }
 560         }
 561
 562 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 563         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 564                 if (el == 3) {
 565                         /*
 566                          * Only use gd->arch.secure_ram if the address is
 567                          * recalculated. Align to 4KB for MMU table.
 568                          */
 569                         /* put page tables in secure ram */
 570                         index = ARRAY_SIZE(final_map) - 2;
 571                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 572                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 573                         final_map[index].phys = final_map[index].virt;
 574                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 575                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 576                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 577                         tlb_addr_save = gd->arch.tlb_addr;
 578                 } else {
 579                         /* Use allocated (board_f.c) memory for TLB */
 580                         tlb_addr_save = gd->arch.tlb_allocated;
 581                         gd->arch.tlb_addr = tlb_addr_save;
 582                 }
 583         }
 584 #endif
 585
 586         /* Reset the fill ptr */
 587         gd->arch.tlb_fillptr = tlb_addr_save;
 588
 589         /* Create normal system page tables */
 590         setup_pgtables();
 591
 592         /* Create emergency page tables */
 593         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 594         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 595         setup_pgtables();
 596         gd->arch.tlb_addr = tlb_addr_save;
 597
 598         /* Disable cache and MMU */
 599         dcache_disable();       /* TLBs are invalidated */
 600         invalidate_icache_all();
 601
 602         /* point TTBR to the new table */
 603         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 604                           MEMORY_ATTRIBUTES);
 605
 606         set_sctlr(get_sctlr() | CR_M);
 607 }
 608
 609 u64 get_page_table_size(void)
 610 {
 611         return 0x10000;
 612 }
 613
 614 int arch_cpu_init(void)
 615 {
 616         /*
 617          * This function is called before U-Boot relocates itself to speed up
 618          * on system running. It is not necessary to run if performance is not
 619          * critical. Skip if MMU is already enabled by SPL or other means.
 620          */
 621         if (get_sctlr() & CR_M)
 622                 return 0;
 623
 624         icache_enable();
 625         __asm_invalidate_dcache_all();
 626         __asm_invalidate_tlb_all();
 627         early_mmu_setup();
 628         set_sctlr(get_sctlr() | CR_C);
 629         return 0;
 630 }
 631
 632 void mmu_setup(void)
 633 {
 634         final_mmu_setup();
 635 }
 636
 637 /*
 638  * This function is called from common/board_r.c.
 639  * It recreates MMU table in main memory.
 640  */
 641 void enable_caches(void)
 642 {
 643         mmu_setup();
 644         __asm_invalidate_tlb_all();
 645         icache_enable();
 646         dcache_enable();
 647 }
 648 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 649
 650 #ifdef CONFIG_TFABOOT
 651 enum boot_src __get_boot_src(u32 porsr1)
 652 {
 653         enum boot_src src = BOOT_SOURCE_RESERVED;
 654         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 655 #if !defined(CONFIG_NXP_LSCH3_2)
 656         u32 val;
 657 #endif
 658         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 659
 660 #if defined(CONFIG_FSL_LSCH3)
 661 #if defined(CONFIG_NXP_LSCH3_2)
 662         switch (rcw_src) {
 663         case RCW_SRC_SDHC1_VAL:
 664                 src = BOOT_SOURCE_SD_MMC;
 665         break;
 666         case RCW_SRC_SDHC2_VAL:
 667                 src = BOOT_SOURCE_SD_MMC2;
 668         break;
 669         case RCW_SRC_I2C1_VAL:
 670                 src = BOOT_SOURCE_I2C1_EXTENDED;
 671         break;
 672         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 673                 src = BOOT_SOURCE_XSPI_NAND;
 674         break;
 675         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 676                 src = BOOT_SOURCE_XSPI_NAND;
 677         break;
 678         case RCW_SRC_RESERVED_1_VAL:
 679                 src = BOOT_SOURCE_RESERVED;
 680         break;
 681         case RCW_SRC_FLEXSPI_NOR_24B:
 682                 src = BOOT_SOURCE_XSPI_NOR;
 683         break;
 684         default:
 685                 src = BOOT_SOURCE_RESERVED;
 686         }
 687 #else
 688         val = rcw_src & RCW_SRC_TYPE_MASK;
 689         if (val == RCW_SRC_NOR_VAL) {
 690                 val = rcw_src & NOR_TYPE_MASK;
 691
 692                 switch (val) {
 693                 case NOR_16B_VAL:
 694                 case NOR_32B_VAL:
 695                         src = BOOT_SOURCE_IFC_NOR;
 696                 break;
 697                 default:
 698                         src = BOOT_SOURCE_RESERVED;
 699                 }
 700         } else {
 701                 /* RCW SRC Serial Flash */
 702                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 703                 switch (val) {
 704                 case RCW_SRC_QSPI_VAL:
 705                 /* RCW SRC Serial NOR (QSPI) */
 706                         src = BOOT_SOURCE_QSPI_NOR;
 707                         break;
 708                 case RCW_SRC_SD_CARD_VAL:
 709                 /* RCW SRC SD Card */
 710                         src = BOOT_SOURCE_SD_MMC;
 711                         break;
 712                 case RCW_SRC_EMMC_VAL:
 713                 /* RCW SRC EMMC */
 714                         src = BOOT_SOURCE_SD_MMC;
 715                         break;
 716                 case RCW_SRC_I2C1_VAL:
 717                 /* RCW SRC I2C1 Extended */
 718                         src = BOOT_SOURCE_I2C1_EXTENDED;
 719                         break;
 720                 default:
 721                         src = BOOT_SOURCE_RESERVED;
 722                 }
 723         }
 724 #endif
 725 #elif defined(CONFIG_FSL_LSCH2)
 726         /* RCW SRC NAND */
 727         val = rcw_src & RCW_SRC_NAND_MASK;
 728         if (val == RCW_SRC_NAND_VAL) {
 729                 val = rcw_src & NAND_RESERVED_MASK;
 730                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 731                         src = BOOT_SOURCE_IFC_NAND;
 732
 733         } else {
 734                 /* RCW SRC NOR */
 735                 val = rcw_src & RCW_SRC_NOR_MASK;
 736                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 737                         src = BOOT_SOURCE_IFC_NOR;
 738                 } else {
 739                         switch (rcw_src) {
 740                         case QSPI_VAL1:
 741                         case QSPI_VAL2:
 742                                 src = BOOT_SOURCE_QSPI_NOR;
 743                                 break;
 744                         case SD_VAL:
 745                                 src = BOOT_SOURCE_SD_MMC;
 746                                 break;
 747                         default:
 748                                 src = BOOT_SOURCE_RESERVED;
 749                         }
 750                 }
 751         }
 752 #endif
 753
 754         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 755                 src = BOOT_SOURCE_QSPI_NOR;
 756
 757         debug("%s: src 0x%x\n", __func__, src);
 758         return src;
 759 }
 760
 761 enum boot_src get_boot_src(void)
 762 {
 763         struct pt_regs regs;
 764         u32 porsr1 = 0;
 765
 766 #if defined(CONFIG_FSL_LSCH3)
 767         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 768 #elif defined(CONFIG_FSL_LSCH2)
 769         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 770 #endif
 771
 772         if (current_el() == 2) {
 773                 regs.regs[0] = SIP_SVC_RCW;
 774
 775                 smc_call(&regs);
 776                 if (!regs.regs[0])
 777                         porsr1 = regs.regs[1];
 778         }
 779
 780         if (current_el() == 3 || !porsr1) {
 781 #ifdef CONFIG_FSL_LSCH3
 782                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 783 #elif defined(CONFIG_FSL_LSCH2)
 784                 porsr1 = in_be32(&gur->porsr1);
 785 #endif
 786         }
 787
 788         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 789
 790         return __get_boot_src(porsr1);
 791 }
 792
 793 #ifdef CONFIG_ENV_IS_IN_MMC
 794 int mmc_get_env_dev(void)
 795 {
 796         enum boot_src src = get_boot_src();
 797         int dev = CONFIG_SYS_MMC_ENV_DEV;
 798
 799         switch (src) {
 800         case BOOT_SOURCE_SD_MMC:
 801                 dev = 0;
 802                 break;
 803         case BOOT_SOURCE_SD_MMC2:
 804                 dev = 1;
 805                 break;
 806         default:
 807                 break;
 808         }
 809
 810         return dev;
 811 }
 812 #endif
 813
 814 enum env_location env_get_location(enum env_operation op, int prio)
 815 {
 816         enum boot_src src = get_boot_src();
 817         enum env_location env_loc = ENVL_NOWHERE;
 818
 819         if (prio)
 820                 return ENVL_UNKNOWN;
 821
 822 #ifdef  CONFIG_ENV_IS_NOWHERE
 823         return env_loc;
 824 #endif
 825
 826         switch (src) {
 827         case BOOT_SOURCE_IFC_NOR:
 828                 env_loc = ENVL_FLASH;
 829                 break;
 830         case BOOT_SOURCE_QSPI_NOR:
 831                 /* FALLTHROUGH */
 832         case BOOT_SOURCE_XSPI_NOR:
 833                 env_loc = ENVL_SPI_FLASH;
 834                 break;
 835         case BOOT_SOURCE_IFC_NAND:
 836                 /* FALLTHROUGH */
 837         case BOOT_SOURCE_QSPI_NAND:
 838                 /* FALLTHROUGH */
 839         case BOOT_SOURCE_XSPI_NAND:
 840                 env_loc = ENVL_NAND;
 841                 break;
 842         case BOOT_SOURCE_SD_MMC:
 843                 /* FALLTHROUGH */
 844         case BOOT_SOURCE_SD_MMC2:
 845                 env_loc =  ENVL_MMC;
 846                 break;
 847         case BOOT_SOURCE_I2C1_EXTENDED:
 848                 /* FALLTHROUGH */
 849         default:
 850                 break;
 851         }
 852
 853         return env_loc;
 854 }
 855 #endif  /* CONFIG_TFABOOT */
 856
 857 u32 initiator_type(u32 cluster, int init_id)
 858 {
 859         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 860         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 861         u32 type = 0;
 862
 863         type = gur_in32(&gur->tp_ityp[idx]);
 864         if (type & TP_ITYP_AV)
 865                 return type;
 866
 867         return 0;
 868 }
 869
 870 u32 cpu_pos_mask(void)
 871 {
 872         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 873         int i = 0;
 874         u32 cluster, type, mask = 0;
 875
 876         do {
 877                 int j;
 878
 879                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 880                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 881                         type = initiator_type(cluster, j);
 882                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 883                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 884                 }
 885                 i++;
 886         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 887
 888         return mask;
 889 }
 890
 891 u32 cpu_mask(void)
 892 {
 893         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 894         int i = 0, count = 0;
 895         u32 cluster, type, mask = 0;
 896
 897         do {
 898                 int j;
 899
 900                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 901                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 902                         type = initiator_type(cluster, j);
 903                         if (type) {
 904                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 905                                         mask |= 1 << count;
 906                                 count++;
 907                         }
 908                 }
 909                 i++;
 910         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 911
 912         return mask;
 913 }
 914
 915 /*
 916  * Return the number of cores on this SOC.
 917  */
 918 int cpu_numcores(void)
 919 {
 920         return hweight32(cpu_mask());
 921 }
 922
 923 int fsl_qoriq_core_to_cluster(unsigned int core)
 924 {
 925         struct ccsr_gur __iomem *gur =
 926                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 927         int i = 0, count = 0;
 928         u32 cluster;
 929
 930         do {
 931                 int j;
 932
 933                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 934                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 935                         if (initiator_type(cluster, j)) {
 936                                 if (count == core)
 937                                         return i;
 938                                 count++;
 939                         }
 940                 }
 941                 i++;
 942         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 943
 944         return -1;      /* cannot identify the cluster */
 945 }
 946
 947 u32 fsl_qoriq_core_to_type(unsigned int core)
 948 {
 949         struct ccsr_gur __iomem *gur =
 950                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 951         int i = 0, count = 0;
 952         u32 cluster, type;
 953
 954         do {
 955                 int j;
 956
 957                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 958                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 959                         type = initiator_type(cluster, j);
 960                         if (type) {
 961                                 if (count == core)
 962                                         return type;
 963                                 count++;
 964                         }
 965                 }
 966                 i++;
 967         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 968
 969         return -1;      /* cannot identify the cluster */
 970 }
 971
 972 #ifndef CONFIG_FSL_LSCH3
 973 uint get_svr(void)
 974 {
 975         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 976
 977         return gur_in32(&gur->svr);
 978 }
 979 #endif
 980
 981 #ifdef CONFIG_DISPLAY_CPUINFO
 982 int print_cpuinfo(void)
 983 {
 984         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 985         struct sys_info sysinfo;
 986         char buf[32];
 987         unsigned int i, core;
 988         u32 type, rcw, svr = gur_in32(&gur->svr);
 989
 990         puts("SoC: ");
 991
 992         cpu_name(buf);
 993         printf(" %s (0x%x)\n", buf, svr);
 994         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 995         get_sys_info(&sysinfo);
 996         puts("Clock Configuration:");
 997         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 998                 if (!(i % 3))
 999                         puts("\n       ");
1000                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1001                 printf("CPU%d(%s):%-4s MHz  ", core,
1002                        type == TY_ITYP_VER_A7 ? "A7 " :
1003                        (type == TY_ITYP_VER_A53 ? "A53" :
1004                        (type == TY_ITYP_VER_A57 ? "A57" :
1005                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1006                        strmhz(buf, sysinfo.freq_processor[core]));
1007         }
1008         /* Display platform clock as Bus frequency. */
1009         printf("\n       Bus:      %-4s MHz  ",
1010                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1011         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1012 #ifdef CONFIG_SYS_DPAA_FMAN
1013         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1014 #endif
1015 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1016         if (soc_has_dp_ddr()) {
1017                 printf("     DP-DDR:   %-4s MT/s",
1018                        strmhz(buf, sysinfo.freq_ddrbus2));
1019         }
1020 #endif
1021         puts("\n");
1022
1023         /*
1024          * Display the RCW, so that no one gets confused as to what RCW
1025          * we're actually using for this boot.
1026          */
1027         puts("Reset Configuration Word (RCW):");
1028         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1029                 rcw = gur_in32(&gur->rcwsr[i]);
1030                 if ((i % 4) == 0)
1031                         printf("\n       %08x:", i * 4);
1032                 printf(" %08x", rcw);
1033         }
1034         puts("\n");
1035
1036         return 0;
1037 }
1038 #endif
1039
1040 #ifdef CONFIG_FSL_ESDHC
1041 int cpu_mmc_init(bd_t *bis)
1042 {
1043         return fsl_esdhc_mmc_init(bis);
1044 }
1045 #endif
1046
1047 int cpu_eth_init(bd_t *bis)
1048 {
1049         int error = 0;
1050
1051 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1052         error = fsl_mc_ldpaa_init(bis);
1053 #endif
1054 #ifdef CONFIG_FMAN_ENET
1055         fm_standard_init(bis);
1056 #endif
1057         return error;
1058 }
1059
1060 static inline int check_psci(void)
1061 {
1062         unsigned int psci_ver;
1063
1064         psci_ver = sec_firmware_support_psci_version();
1065         if (psci_ver == PSCI_INVALID_VER)
1066                 return 1;
1067
1068         return 0;
1069 }
1070
1071 static void config_core_prefetch(void)
1072 {
1073         char *buf = NULL;
1074         char buffer[HWCONFIG_BUFFER_SIZE];
1075         const char *prefetch_arg = NULL;
1076         size_t arglen;
1077         unsigned int mask;
1078         struct pt_regs regs;
1079
1080         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1081                 buf = buffer;
1082         else
1083                 return;
1084
1085         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1086                                          &arglen, buf);
1087
1088         if (prefetch_arg) {
1089                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1090                 if (mask & 0x1) {
1091                         printf("Core0 prefetch can't be disabled\n");
1092                         return;
1093                 }
1094
1095 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1096                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1097                 regs.regs[1] = mask;
1098                 smc_call(&regs);
1099
1100                 if (regs.regs[0])
1101                         printf("Prefetch disable config failed for mask ");
1102                 else
1103                         printf("Prefetch disable config passed for mask ");
1104                 printf("0x%x\n", mask);
1105         }
1106 }
1107
1108 #ifdef CONFIG_PCIE_ECAM_GENERIC
1109 __weak void set_ecam_icids(void)
1110 {
1111 }
1112 #endif
1113
1114 int arch_early_init_r(void)
1115 {
1116 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1117         u32 svr_dev_id;
1118         /*
1119          * erratum A009635 is valid only for LS2080A SoC and
1120          * its personalitiesi
1121          */
1122         svr_dev_id = get_svr();
1123         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1124                 erratum_a009635();
1125 #endif
1126 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1127         erratum_a009942_check_cpo();
1128 #endif
1129         if (check_psci()) {
1130                 debug("PSCI: PSCI does not exist.\n");
1131
1132                 /* if PSCI does not exist, boot secondary cores here */
1133                 if (fsl_layerscape_wake_seconday_cores())
1134                         printf("Did not wake secondary cores\n");
1135         }
1136
1137         config_core_prefetch();
1138
1139 #ifdef CONFIG_SYS_HAS_SERDES
1140         fsl_serdes_init();
1141 #endif
1142 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1143         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1144          * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1145          * EC*_PMUX(rgmii) bits in RCW.
1146          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1147          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1148          * Now if a dpmac is enabled by serdes bits then it takes precedence
1149          * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1150          * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1151          * then the dpmac is SGMII and not RGMII.
1152          *
1153          * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1154          * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1155          * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1156          * then don't enable it.
1157          */
1158         fsl_rgmii_init();
1159 #endif
1160 #ifdef CONFIG_FMAN_ENET
1161 #ifndef CONFIG_DM_ETH
1162         fman_enet_init();
1163 #endif
1164 #endif
1165 #ifdef CONFIG_SYS_DPAA_QBMAN
1166         setup_qbman_portals();
1167 #endif
1168 #ifdef CONFIG_PCIE_ECAM_GENERIC
1169         set_ecam_icids();
1170 #endif
1171         return 0;
1172 }
1173
1174 int timer_init(void)
1175 {
1176         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1177 #ifdef CONFIG_FSL_LSCH3
1178         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1179 #endif
1180 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1181         defined(CONFIG_ARCH_LS1028A)
1182         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1183         u32 svr_dev_id;
1184 #endif
1185 #ifdef COUNTER_FREQUENCY_REAL
1186         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1187
1188         /* Update with accurate clock frequency */
1189         if (current_el() == 3)
1190                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1191 #endif
1192
1193 #ifdef CONFIG_FSL_LSCH3
1194         /* Enable timebase for all clusters.
1195          * It is safe to do so even some clusters are not enabled.
1196          */
1197         out_le32(cltbenr, 0xf);
1198 #endif
1199
1200 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1201         defined(CONFIG_ARCH_LS1028A)
1202         /*
1203          * In certain Layerscape SoCs, the clock for each core's
1204          * has an enable bit in the PMU Physical Core Time Base Enable
1205          * Register (PCTBENR), which allows the watchdog to operate.
1206          */
1207         setbits_le32(pctbenr, 0xff);
1208         /*
1209          * For LS2080A SoC and its personalities, timer controller
1210          * offset is different
1211          */
1212         svr_dev_id = get_svr();
1213         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1214                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1215
1216 #endif
1217
1218         /* Enable clock for timer
1219          * This is a global setting.
1220          */
1221         out_le32(cntcr, 0x1);
1222
1223         return 0;
1224 }
1225
1226 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1227
1228 void __efi_runtime reset_cpu(ulong addr)
1229 {
1230         u32 val;
1231
1232 #ifdef CONFIG_ARCH_LX2160A
1233         val = in_le32(rstcr);
1234         val |= 0x01;
1235         out_le32(rstcr, val);
1236 #else
1237         /* Raise RESET_REQ_B */
1238         val = scfg_in32(rstcr);
1239         val |= 0x02;
1240         scfg_out32(rstcr, val);
1241 #endif
1242 }
1243
1244 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1245
1246 void __efi_runtime EFIAPI efi_reset_system(
1247                        enum efi_reset_type reset_type,
1248                        efi_status_t reset_status,
1249                        unsigned long data_size, void *reset_data)
1250 {
1251         switch (reset_type) {
1252         case EFI_RESET_COLD:
1253         case EFI_RESET_WARM:
1254         case EFI_RESET_PLATFORM_SPECIFIC:
1255                 reset_cpu(0);
1256                 break;
1257         case EFI_RESET_SHUTDOWN:
1258                 /* Nothing we can do */
1259                 break;
1260         }
1261
1262         while (1) { }
1263 }
1264
1265 efi_status_t efi_reset_system_init(void)
1266 {
1267         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1268 }
1269
1270 #endif
1271
1272 /*
1273  * Calculate reserved memory with given memory bank
1274  * Return aligned memory size on success
1275  * Return (ram_size + needed size) for failure
1276  */
1277 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1278 {
1279         phys_size_t ram_top = ram_size;
1280
1281 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1282         ram_top = mc_get_dram_block_size();
1283         if (ram_top > ram_size)
1284                 return ram_size + ram_top;
1285
1286         ram_top = ram_size - ram_top;
1287         /* The start address of MC reserved memory needs to be aligned. */
1288         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1289 #endif
1290
1291         return ram_size - ram_top;
1292 }
1293
1294 phys_size_t get_effective_memsize(void)
1295 {
1296         phys_size_t ea_size, rem = 0;
1297
1298         /*
1299          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1300          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1301          * allocated from first region. If the memory extends to  the second
1302          * region (or the third region if applicable), Management Complex (MC)
1303          * memory should be put into the highest region, i.e. the end of DDR
1304          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1305          * U-Boot doesn't relocate itself into higher address. Should DDR be
1306          * configured to skip the first region, this function needs to be
1307          * adjusted.
1308          */
1309         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1310                 ea_size = CONFIG_MAX_MEM_MAPPED;
1311                 rem = gd->ram_size - ea_size;
1312         } else {
1313                 ea_size = gd->ram_size;
1314         }
1315
1316 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1317         /* Check if we have enough space for secure memory */
1318         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1319                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1320         else
1321                 printf("Error: No enough space for secure memory.\n");
1322 #endif
1323         /* Check if we have enough memory for MC */
1324         if (rem < board_reserve_ram_top(rem)) {
1325                 /* Not enough memory in high region to reserve */
1326                 if (ea_size > board_reserve_ram_top(ea_size))
1327                         ea_size -= board_reserve_ram_top(ea_size);
1328                 else
1329                         printf("Error: No enough space for reserved memory.\n");
1330         }
1331
1332         return ea_size;
1333 }
1334
1335 #ifdef CONFIG_TFABOOT
1336 phys_size_t tfa_get_dram_size(void)
1337 {
1338         struct pt_regs regs;
1339         phys_size_t dram_size = 0;
1340
1341         regs.regs[0] = SMC_DRAM_BANK_INFO;
1342         regs.regs[1] = -1;
1343
1344         smc_call(&regs);
1345         if (regs.regs[0])
1346                 return 0;
1347
1348         dram_size = regs.regs[1];
1349         return dram_size;
1350 }
1351
1352 static int tfa_dram_init_banksize(void)
1353 {
1354         int i = 0, ret = 0;
1355         struct pt_regs regs;
1356         phys_size_t dram_size = tfa_get_dram_size();
1357
1358         debug("dram_size %llx\n", dram_size);
1359
1360         if (!dram_size)
1361                 return -EINVAL;
1362
1363         do {
1364                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1365                 regs.regs[1] = i;
1366
1367                 smc_call(&regs);
1368                 if (regs.regs[0]) {
1369                         ret = -EINVAL;
1370                         break;
1371                 }
1372
1373                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1374                       regs.regs[2]);
1375                 gd->bd->bi_dram[i].start = regs.regs[1];
1376                 gd->bd->bi_dram[i].size = regs.regs[2];
1377
1378                 dram_size -= gd->bd->bi_dram[i].size;
1379
1380                 i++;
1381         } while (dram_size);
1382
1383         if (i > 0)
1384                 ret = 0;
1385
1386 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1387         /* Assign memory for MC */
1388 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1389         if (gd->bd->bi_dram[2].size >=
1390             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1391                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1392                             gd->bd->bi_dram[2].size -
1393                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1394         } else
1395 #endif
1396         {
1397                 if (gd->bd->bi_dram[1].size >=
1398                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1399                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1400                                 gd->bd->bi_dram[1].size -
1401                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1402                 } else if (gd->bd->bi_dram[0].size >
1403                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1404                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1405                                 gd->bd->bi_dram[0].size -
1406                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1407                 }
1408         }
1409 #endif  /* CONFIG_RESV_RAM */
1410
1411         return ret;
1412 }
1413 #endif
1414
1415 int dram_init_banksize(void)
1416 {
1417 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1418         phys_size_t dp_ddr_size;
1419 #endif
1420
1421 #ifdef CONFIG_TFABOOT
1422         if (!tfa_dram_init_banksize())
1423                 return 0;
1424 #endif
1425         /*
1426          * gd->ram_size has the total size of DDR memory, less reserved secure
1427          * memory. The DDR extends from low region to high region(s) presuming
1428          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1429          * the location of secure memory. gd->arch.resv_ram tracks the location
1430          * of reserved memory for Management Complex (MC). Because gd->ram_size
1431          * is reduced by this function if secure memory is reserved, checking
1432          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1433          */
1434
1435 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1436         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1437                 debug("No need to run again, skip %s\n", __func__);
1438
1439                 return 0;
1440         }
1441 #endif
1442
1443         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1444         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1445                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1446                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1447                 gd->bd->bi_dram[1].size = gd->ram_size -
1448                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1449 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1450                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1451                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1452                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1453                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1454                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1455                 }
1456 #endif
1457         } else {
1458                 gd->bd->bi_dram[0].size = gd->ram_size;
1459         }
1460 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1461         if (gd->bd->bi_dram[0].size >
1462                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1463                 gd->bd->bi_dram[0].size -=
1464                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1465                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1466                                       gd->bd->bi_dram[0].size;
1467                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1468                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1469         }
1470 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1471
1472 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1473         /* Assign memory for MC */
1474 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1475         if (gd->bd->bi_dram[2].size >=
1476             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1477                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1478                             gd->bd->bi_dram[2].size -
1479                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1480         } else
1481 #endif
1482         {
1483                 if (gd->bd->bi_dram[1].size >=
1484                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1485                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1486                                 gd->bd->bi_dram[1].size -
1487                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1488                 } else if (gd->bd->bi_dram[0].size >
1489                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1490                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1491                                 gd->bd->bi_dram[0].size -
1492                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1493                 }
1494         }
1495 #endif  /* CONFIG_RESV_RAM */
1496
1497 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1498 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1499 #error "This SoC shouldn't have DP DDR"
1500 #endif
1501         if (soc_has_dp_ddr()) {
1502                 /* initialize DP-DDR here */
1503                 puts("DP-DDR:  ");
1504                 /*
1505                  * DDR controller use 0 as the base address for binding.
1506                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1507                  */
1508                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1509                                           CONFIG_DP_DDR_CTRL,
1510                                           CONFIG_DP_DDR_NUM_CTRLS,
1511                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1512                                           NULL, NULL, NULL);
1513                 if (dp_ddr_size) {
1514                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1515                         gd->bd->bi_dram[2].size = dp_ddr_size;
1516                 } else {
1517                         puts("Not detected");
1518                 }
1519         }
1520 #endif
1521
1522 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1523         debug("%s is called. gd->ram_size is reduced to %lu\n",
1524               __func__, (ulong)gd->ram_size);
1525 #endif
1526
1527         return 0;
1528 }
1529
1530 #if CONFIG_IS_ENABLED(EFI_LOADER)
1531 void efi_add_known_memory(void)
1532 {
1533         int i;
1534         phys_addr_t ram_start;
1535         phys_size_t ram_size;
1536
1537         /* Add RAM */
1538         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1539 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1540 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1541 #error "This SoC shouldn't have DP DDR"
1542 #endif
1543                 if (i == 2)
1544                         continue;       /* skip DP-DDR */
1545 #endif
1546                 ram_start = gd->bd->bi_dram[i].start;
1547                 ram_size = gd->bd->bi_dram[i].size;
1548 #ifdef CONFIG_RESV_RAM
1549                 if (gd->arch.resv_ram >= ram_start &&
1550                     gd->arch.resv_ram < ram_start + ram_size)
1551                         ram_size = gd->arch.resv_ram - ram_start;
1552 #endif
1553                 efi_add_memory_map(ram_start, ram_size,
1554                                    EFI_CONVENTIONAL_MEMORY);
1555         }
1556 }
1557 #endif
1558
1559 /*
1560  * Before DDR size is known, early MMU table have DDR mapped as device memory
1561  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1562  * needs to be set for these mappings.
1563  * If a special case configures DDR with holes in the mapping, the holes need
1564  * to be marked as invalid. This is not implemented in this function.
1565  */
1566 void update_early_mmu_table(void)
1567 {
1568         if (!gd->arch.tlb_addr)
1569                 return;
1570
1571         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1572                 mmu_change_region_attr(
1573                                         CONFIG_SYS_SDRAM_BASE,
1574                                         gd->ram_size,
1575                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1576                                         PTE_BLOCK_OUTER_SHARE           |
1577                                         PTE_BLOCK_NS                    |
1578                                         PTE_TYPE_VALID);
1579         } else {
1580                 mmu_change_region_attr(
1581                                         CONFIG_SYS_SDRAM_BASE,
1582                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1583                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1584                                         PTE_BLOCK_OUTER_SHARE           |
1585                                         PTE_BLOCK_NS                    |
1586                                         PTE_TYPE_VALID);
1587 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1588 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1589 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1590 #endif
1591                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1592                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1593                         mmu_change_region_attr(
1594                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1595                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1596                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1597                                         PTE_BLOCK_OUTER_SHARE           |
1598                                         PTE_BLOCK_NS                    |
1599                                         PTE_TYPE_VALID);
1600                         mmu_change_region_attr(
1601                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1602                                         gd->ram_size -
1603                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1604                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1605                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1606                                         PTE_BLOCK_OUTER_SHARE           |
1607                                         PTE_BLOCK_NS                    |
1608                                         PTE_TYPE_VALID);
1609                 } else
1610 #endif
1611                 {
1612                         mmu_change_region_attr(
1613                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1614                                         gd->ram_size -
1615                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1616                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1617                                         PTE_BLOCK_OUTER_SHARE           |
1618                                         PTE_BLOCK_NS                    |
1619                                         PTE_TYPE_VALID);
1620                 }
1621         }
1622 }
1623
1624 __weak int dram_init(void)
1625 {
1626         fsl_initdram();
1627 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1628         defined(CONFIG_SPL_BUILD)
1629         /* This will break-before-make MMU for DDR */
1630         update_early_mmu_table();
1631 #endif
1632
1633         return 0;
1634 }
1635
1636 #ifdef CONFIG_ARCH_MISC_INIT
1637 __weak int serdes_misc_init(void)
1638 {
1639         return 0;
1640 }
1641
1642 int arch_misc_init(void)
1643 {
1644         serdes_misc_init();
1645
1646         return 0;
1647 }
1648 #endif